42
Page 3
T5CD2
1.2 Pin Assignment Diagram
Figure 1-1 Pin Assignment
VREFH
T5CD2
LQFP100
TOPVIEW
1
5
10
15
20
25
3
0
3
5
4
0
4
5
5
0
55
60
65
70
75
8
0
8
5
9
0
9
5
1
00
AVSS
P70/TA0IN
P71/TA1OUT
P72/TA3OUT
P73/TA4IN
P74/TA5OUT
P75/INT0
P80/TB0IN0/INT5
P81/TB0IN1/INT6
AVCC
P82/TB0OUT0
P83/TB0OUT1
P84/TB1IN0/INT7
P85/TB1IN1/INT8
P86/TB1OUT0
P87/TB1OUT1
P90/TXD0
P91/RXD0
P92/SCLK0/CTS0
P93/TXD1
P95/SCLK1/CTS1
DVCC
P30/TB3IN0/INT3/SDA0
PZ3/R/W
PZ2/HWR
PZ1/WR
PZ0/RD
P27/A7/A23
P26/A6/A22
P25/A5/A21
P24/A4/A20
P23/A3/A19
P22/A2/A18
DVCC
NMI
DVSS
P21/A1/A17
P20/A0/A16
P17/AD15/A15
P16/AD14/A14
P15/AD13/A13
P14/AD12/A12
P13/AD11/A11
P12/AD10/A10
P11/AD9/A9
P10/AD8/A8
P07/AD7
P
06
/A
D
6
P
05
/A
D
5
P
04
/A
D
4
P
03
/A
D
3
P
02
/A
D
2
P
01
/A
D
1
P
00
/A
D
0
P
44
/A
LE
P
43
/C
S3
/S
C
LK
2/
C
TS
2
P42/CS2/RXD2
P
41
/C
S1
/T
X
D
2
P
40
/C
S
0/
S
C
O
U
T
PA3
/T
B2
O
U
T1
PA2
/T
B
2O
U
T0
PA1
/T
B
2I
N
1/
IN
T2
PA0
/T
B
2I
N
0/
IN
T1
E
M
U
1
B
O
O
T/
EM
U
0
P
97
/X
T2
P
96
/X
T1
RESET
AM
1
X1
D
V
S
S
X
2
P
60
/A
N
8
P
65
/A
N
13
P
57
/A
N
7
P
61
/A
N
9
P
62
/A
N
10
P
63
/A
N
11
P
64
/A
N
12
P
55
/A
N
5
P
66
/A
N
14
P
67
/A
N
15
P
53
/A
N
3
P
52
/A
N
2
P
51
/A
N
1
P
50
/A
N
0
D
V
S
S
D
V
C
C
P
B
3/
TB
4O
U
T1
P
B
2/
TB
4O
U
T0
PB1
/TB4IN1
/INT
10
/SCL
1
PB0
/TB4IN0
/INT
9/
SDA1
P
33
/T
B
3O
U
T1
P
32
/W
AI
T/
TB
3O
U
T0
AM0
P
31
/T
B
3I
N
1/
IN
T4
/S
C
L0
P
56
/A
N
6
P94/RXD1
P
54
/A
N
4
Page 4
1.3 Block Diagram
T5CD2
1.3 Block Diagram
Figure 1-2 Block Diagram
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12. MICROPROCESSOR AND IC DATA
IC21 : T5CD2