22
21
UPDATE
RST/ST+5V/GND
D
MO
F
MO
TR+/-
FC+/-
LOGIC
CONTROL
SPINDLE-
SLED+
SLED-
T
R
A
C
K
IN
G
+
T
R
A
C
K
IN
G
-
F
O
C
U
S
+
F
O
C
U
S
-
SPINDLE MOTOR
SLED MOTOR
SPINDLE-
SLED-
SLED+
LIMIT SW
CL/SW
COM
20Mhz
LOADING-
SERIAL
PORT
VOLUME
Control
MIXER
VOLUME
Control
INTERPOLATION
FILTER
FILTER
INTERPOLATION
DAC
DAC
ANALOG
FILTER
FILTER
ANALOG
MODE
Selector
Control
Port
SDATA
SCLK
LRCK
DAC_MCK
NC (DAC_SDA)
NC
NC
NC (DAC_SCL)
AOUTB-
AOUTB+
AOUTA+
AOUTA-
MDI
LDO
EXTERNAL
Mute Control
Reference
CMOUT FILT+
D
O
U
T
+3.3VA
SIO/UART
(SIO0)
SIO/UART
SIO/UART
(SIO1)
(SIO2)
I2C
I2C
(SBIO)
(SBI1)
8bit TIMER
8bit TIMER
8bit TIMER
8bit TIMER
8bit TIMER
8bit TIMER
(TMRA0)
(TMRA1)
(TMRA2)
(TMRA3)
(TMRA4)
(TMRA5)
(TMRB0)
16Bit TIMER
16Bit TIMER
16Bit TIMER
16Bit TIMER
16Bit TIMER
(TMRB1)
(TMRB2)
(TMRB3)
(TMRB4)
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
W
B
D
H
A
C
E
L
IX
1Y
IZ
SP
32bit
F
P C
WATCH-DOG TIMER
Clock Timer
8 K B R A M
900/L1 CPU
High-speed
Oscillator
Oscillator
LOW-speed
MODE
CONTROLLER
INTERRUPT
CONTROLLER
INTERRUPT
CONTROLLER
DATA BUS
ADDRESS BUS
Memory
Controller
(blocks)
P O R T
1 0 - B I T
1 6 C H
A D
RL4
RL3
RL1
RL2
RL5
E
C
B
F
D
A
DAC_MCK DSP_MCK
PLL_SCL
PLL_SDA
DECODER
256X 1024
MEMORY ARRAY
COLUMN I/O
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
A0-A14
VCC
GND
I/O1-I/O7
CE1
OE
WE
V
F
D
-C
LK
V
F
D
-C
E
V
F
D
-D
I
V
F
D
-P
O
W
E
R
REMO
V
F
D
-C
LK
V
F
D
-C
E
V
F
D
-D
I
V
F
D
-P
O
W
E
R
RS/REMOTE_IN
RS/REMOTE_IN
SRAM_CE
SRAM_OE
SRAM_WE
ADDRESS PORT
DATA PORT
RST
ST+5V
D
A
C
_R
S
T
DAC_RST
P
LL
_S
D
A
P
LL
_S
C
L
+5VA
K
E
Y
D
A
T
A
LE
D
D
A
T
A
K
E
Y
D
A
T
A
LE
D
D
A
T
A
CD-BUS2
CD-BUS3
CD-BUCK
CD-CCE
CD-RST
M
T
-S
T
B
Y
C
L-
M
O
P
-M
O
P
-S
W
C
L-
S
W
LI
M
IT
-S
W
O
P
-M
C
L-
M
M
T
-S
T
B
Y
OP/SW
O
P
-S
W
C
L-
S
W
LI
M
IT
-S
W
SYS_DETECT
ST+5V
EXTERNAL
INTERNAL
H
L
S
Y
S
_D
E
T
E
C
T
S
D
A
T
A
S
C
LK
LR
C
K
DSP_MCK
D
MO
F
MO
T
R
O
F
O
O
T
R
O
F
O
O
F
O
C
U
S
-
F
O
C
U
S
+
T
R
A
C
K
IN
G
-
T
R
A
C
K
IN
G
+
E
F
B
D
A
C
+3.3VA
+5VA
16.9344 MHz
ST+5V
ST+5V
+P1.5V
+3.3V
3.3VDA
+VREF
+RF3.3V
+VREF
+VREF
+8V
A_MUTE
B_MUTE
+12V -12V
F_MUTE
A_MUTE
B_MUTE
F_MUTE
+3.3VCL
P_MUTE
P_MUTE
FL+/-
FVDD
VP FST+5V
+12V
-12V
A
B
VDD
VDD
IN
T
E
RR
U
P
T
89
PLL_SCL
PLL_SDA
ST+5V
P
W
R
_D
T
_O
N
/O
F
F
CMOS
LV
Divider
and
Output
Control
Programming
and
Control Register
+1.8V +3.3VCL
TC7WHU04FU
+3.3VCL
CMOS
LV
CMOS
LV
V
D
IS
G
N
D
VOUT
VIN
GND
OUT
IN
3
2
1
NC
OUT
D
S
VSS
VDD
GND
OUT
IN
GND
OUT
IN
AUDIO+
AUDIO+
AUDIO-
+8V
VDD
+3.3V
3.3VDA
+P1.5V
VP
FL+
FL-
+8V
+8V
ST+5V
REMO
RS_REMOTE_IN
PWR_MUTE
B+
+3.3V
+1.8V
u-COM
26
28
21 22 33
57 58 59 61 65 67
4
5
6
UPDATE PORT
44~
9~
52
53
54
55
56
92
90
SRAM
20 19
71 75 78
R A M
R A M
FLASH ROM 128KByte
ROM Correction
18 68 35
30
79 80 81
38
85
86
87
76
41
9
88
EEPROM
31
32
3
2
5
4
1
WELCOME
CLOCK(PLL+VCO)
DSP POWER
CDCE913
9
10
12
13
23
40
41
42
43
37
61
91
92
94
95
96
97
98
100
62 63 64
TC94A70FG
CD DSP
35
33
34
OPTICAL OUT
COAXIAL OUT
C
D
M
E
C
H
A
N
IS
M
SYS DETECT
DRIVE I.C
M
M
M
L
R
LPF (OP Amp IC)
HEADPHONE
OUTPUT
BUS IN/OUT
UPDATE PORT
ANALOG L
ANALOG R
+
Tr.Buffer
FLUSHER IN(U Ver ONLY)
PLL
with SSC
DAC (CS4392)
VCXO
XO
LVCMOS
EEPROM
3
2
1
3
2
1
3
2
1
4
3
2
1
3
2
1
3
2
1
MAIN TRANS
SUB TRANS
3
2
1
3
2
1
CD-RF
IN
CD-RF
Amp
Audio
DAC
Analog
Post
Filter
Servo
ADC
CDP
DSP
24-Bit
DSP
1 Mbit
SRAM
Servo
Processor
Servo
DAC
Peripheral
I/F
PLL/VCO
(Audio Out)
3.3V
1.5V
8. BLOCK DIAGRAM
