LSI LSI53C1030, Technical Manual

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4-4 PCI Host Register Description
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
SERR/ Enable 8
Setting this bit enables the LSI53C1030 to activate the
SERR/ driver. Clearing this bit disables the SERR/ driver.
Reserved 7
This bit is reserved.
Enable Parity Error Response 6
Setting this bit enables the LSI53C1030 PCI function to
detect parity errors on the PCI bus and report these
errors to the system. Clearing this bit causes the
LSI53C1030 PCI function to set the Detected Parity Error
bit, bit 15 in the PCI
Status register, but not assert PERR/
when the PCI function detects a parity error. This bit only
affects parity checking. The PCI function always gener-
ates parity for the PCI bus.
Reserved 5
This bit is reserved.
Write and Invalidate Enable 4
Setting this bit enables the PCI function to generate write
and invalidate commands on the PCI bus when operating
in the conventional PCI mode.
Reserved 3
This bit is reserved.
Enable Bus Mastering 2
Setting this bit allows the PCI function to behave as a PCI
bus master. Clearing this bit disables the PCI function
from generating PCI bus master accesses.
Enable Memory Space 1
This bit controls the ability of the PCI function to respond
to Memory Space accesses. Setting this bit allows the
LSI53C1030 to respond to Memory Space accesses at
the address range specified by the
Memory [0] Low ,
Memory [0] High , Memory [1] Low , Memory [1] High , and
Expansion ROM Base Address registers. Clearing this bit
disables the PCI function’s response to PCI Memory
Space accesses.
Enable I/O Space 0
This bit controls the LSI53C1030 PCI function’s response
to I/O Space accesses. Setting this bit enables the PCI