LSI LSI53C1030, Technical Manual

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4-26 PCI Host Register Description
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Maximum Memory Read Byte Count [3:2]
These bits indicate the maximum byte count the
LSI53C1030 uses when initiating a sequence with one of
the burst memory read commands.
Table 4.5 provides
the bit encodings for this field.
Reserved 1
This bit is reserved.
Data Parity Error Recovery Enable 0
The host device driver sets this bit to allow the
LSI53C1030 to attempt to recover from data parity errors.
If the user clears this bit and the LSI53C1030 is operating
in the PCI-X mode, the LSI53C1030 asserts SERR/
whenever the Master Data Parity Error bit in the PCI
Sta-
tus register is set.
0b010 3
0b011 4
0b100 8
0b101 Reserved
0b110 Reserved
0b111 Reserved
Table 4.5 Maximum Memory Read Count
Bits [3:2]
Encoding
Maximum Memory Read
Byte Count
0b00 512
0b01 1024
0b10 2048
0b11 Reserved
Table 4.4 Maximum Outstanding Split Transactions (Cont.)
Bits [6:4]
Encoding
Maximum Outstanding
Split Transactions