4-16
PCI Host Register Description
Version 2.1
Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Register: 0x38–0x3B
Reserved
Reserved
[31:0]
This register is reserved.
Register: 0x3C
Interrupt Line
Read/Write
Interrupt Line
[7:0]
This register communicates interrupt line routing informa-
tion. Power-On-Self-Test (POST) software writes the rout-
ing information into this register as it configures the
system. This register indicates the system interrupt con-
troller input to which this PCI function’s interrupt pin con-
nects. System architecture determines the values in this
register.
Register: 0x3D
Interrupt Pin
Read Only
Interrupt Pin
[7:0]
The encoding of this read only register is unique to each
function on the LSI53C1030. It indicates which interrupt
pin the function uses. The value for Function [0] is 0x01,
31
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
Interrupt Line
0
0
0
0
0
0
0
0
7
0
Function [0] Interrupt Pin
0
0
0
0
0
0
0
1
Function [1] Interrupt Pin
0
0
0
0
0
0
1
0
Summary of Contents for LSI53C1030
Page 6: ...vi Preface Version 2 1 Copyright 2001 2002 2003 by LSI Logic Corporation All rights reserved...
Page 10: ...x Contents Version 2 1 Copyright 2001 2002 2003 by LSI Logic Corporation All rights reserved...
Page 12: ...xii Version 2 1 Copyright 2001 2002 2003 by LSI Logic Corporation All rights reserved...
Page 16: ...xvi Version 2 1 Copyright 2001 2002 2003 by LSI Logic Corporation All rights reserved...
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