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This Data Sheet may be revised by subsequent versions ©2003 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

30

EN29F040A

Rev. B, Issue Date: 2004/04/01

SWITCHING WAVEFORMS (continued)

Figure 10. Alternate /CE

Controlled Write Operation Timings

Notes:

1.  PA is address of the memory location to be programmed.
2.  PD is data to be programmed at byte address.
3.  /DQ7 is the output of the complement of the data written to the device.
4. D

OUT

is the output of data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

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Summary of Contents for EN29F040A

Page 1: ...Resume modes Read and program another Sector during Erase Suspend Mode 0 23 µm triple metal double poly triple well CMOS Flash Technology Low Vcc write inhibit 3 2V 100K endurance cycle Package Options 32 pin PDIP 32 pin PLCC 32 pin TSOP Type 1 Commercial and Industrial Temperature Ranges GENERAL DESCRIPTION The EN29F040A is a 4 Megabit electrically erasable read write non volatile flash memory Or...

Page 2: ...e Function A0 A18 Addresses DQ0 DQ7 Data Inputs Outputs CE Chip Enable OE Output Enable W E Write Enable Vcc Supply Voltage 5V 10 Vss Ground TABLE 2 SECTOR ARCHITECTURE Sector ADDRESSES SIZE Kbytes A18 A17 A16 7 70000h 7FFFFh 64 1 1 1 6 60000h 6FFFFh 64 1 1 0 5 50000h 5FFFFh 64 1 0 1 4 40000h 4FFFFh 64 1 0 0 3 30000h 3FFFFh 64 0 1 1 2 20000h 2FFFFh 64 0 1 0 1 10000h 1FFFFh 64 0 0 1 0 00000h 0FFFFh...

Page 3: ...ecifications 3 EN29F040A Rev B Issue Date 2004 04 01 BLOCK DIAGRAM WE CE OE State Control Command Register Erase Voltage Generator Input Output Buffers Program Voltage Generator Chip Enable Output Enable Logic Data Latch Y Decoder X Decoder Y Gating Cell Matrix Timer Vcc Detector A0 A18 Vcc Vss DQ0 DQ7 Address Latch Block Protect Switches STB STB ...

Page 4: ...be revised by subsequent versions 2003 Eon Silicon Solution Inc www essi com tw or modifications due to changes in technical specifications 4 EN29F040A Rev B Issue Date 2004 04 01 FIGURE 2 PDIP FIGURE 3 PLCC FIGURE 4 TSOP ...

Page 5: ...ID X L X H L X CODE SECTOR PROTECTION L Pulse L VID VID X L X X X X X VERIFY SECTOR UNPROTECTION L H L VID X H X H L X CODE SECTOR UNPROTECTION Pulse L VID VID L X X H X X X X WRITE L L H A9 A8 A6 A5 A1 A0 Ax y DIN 0 7 NOTES 1 L VIL H VIH VID 11 0V 0 5V 2 X Don t care either VIH or VIL 3 Ax y Ax Addr x Ay Addr y TABLE 4 DEVICE IDENTIFICTION 4M FLASH MANUFACTURER DEVICE ID TABLE A8 A6 A1 A0 DQ 7 0 ...

Page 6: ...oselect mode See Reset Command section See also Requirements for Reading Array Data in the Device Bus Operations section for more information The Read Operations table provides the read parameters and Read Operation Timings diagram shows the timing diagram Output Disable Mode When the OE pin is at a logic high level VIH the output from the EN29F040A is disabled The output pins are placed in a high...

Page 7: ...am set up command The program address and data are written next which in turn initiate the Embedded Program algorithm The system is not required to provide further controls or timings The device automatically provides internally generated program pulses and verifies the programmed cell margin Table 5 Command Definitions shows the address and data requirements for the byte program command sequence ...

Page 8: ...ected sector and 01h for a protected sector Byte Programming Command Programming the EN29F040A is performed on a byte by byte basis using a four bus cycle operation two unlock write cycles followed by the Program Setup command and Program Data Write cycle When the program command is executed no additional CPU controls or timings are necessary An internal timer terminates the program operation auto...

Page 9: ...end command is valid All other commands are ignored When the Embedded Erase algorithm is complete the device returns to reading array data and addresses are no longer latched The system can determine the status of the erase operation by using DQ7 DQ6 or DQ2 Refer to Write Operation Status for information on these status bits Flowchart 4 illustrates the algorithm for the erase operation Refer to th...

Page 10: ...and are ignored Another Erase Suspend command can be written after the device has resumed erasing Sector Protection Unprotection The hardware sector protection feature disables both program and erase operations in any sector The hardware sector unprotection feature re enables both program and erase operations in previously protected sectors Sector protection unprotection must be implemented using ...

Page 11: ...rwise DATA polling may give an inaccurate result if the address used is in a protected sector Just prior to the completion of the embedded operations DQ7 may change asynchronously when the output enable OE is low This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time Depending on when the system samples the DQ7 output it ma...

Page 12: ...is actively erasing that is the Embedded Erase algorithm is in progress or whether that sector is erase suspended Toggle Bit II is valid after the rising edge of the final WE pulse in the command sequence DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure The system may use either OE or CE to control the read cycles But DQ2 cannot distinguish wh...

Page 13: ...finition 1 Erase Complete or erase Sector in Erase suspend 0 Erase On Going DQ7 Program Complete or data of non erase Sector during Erase Suspend 7 DATA POLLING DQ7 Program On Going 1 0 1 0 1 0 1 Erase or Program On going DQ6 Read during Erase Suspend 6 TOGGLE BIT 1 1 1 1 1 1 1 Erase Complete 1 Program or Erase Error 5 ERROR BIT 0 Program or Erase On going 1 0 1 0 1 0 1 Chip Erase Sector Erase or ...

Page 14: ...l reset to the READ mode Subsequent writes will be ignored until VCC VLKO Write Noise Pulse Protection Noise pulses less than 5ns on OE CE or WE will neither initiate a write cycle nor change the command register Logical Inhibit If CE VIH or WE VIH writing is inhibited To initiate a write cycle CE and W E must be a logical zero If CE W E and OE are all logical zero not recommended usage it will be...

Page 15: ...N29F040A Rev B Issue Date 2004 04 01 EMBEDDED ALGORITHMS Flowchart 1 Embedded Program START Write Program Command Sequence shown below Data Poll Device Last Address Programming Done Increment Address No Yes Flowchart 2 Embedded Program Command Sequence See the Command Definitions section for more information 2AAH 55H 555H AAH 555H A0H PROGRAM ADDRESS PROGRAM DATA ...

Page 16: ... Solution Inc www essi com tw or modifications due to changes in technical specifications 16 EN29F040A Rev B Issue Date 2004 04 01 Flowchart 3 Embedded Erase START Write Erase Command Sequence shown below Data Polling Device or Toggle Bit Successfully Completed ERASE Done ...

Page 17: ...to changes in technical specifications 17 EN29F040A Rev B Issue Date 2004 04 01 Flowchart 4 Embedded Erase Command Sequence See the Command Definitions section for more information Chip Erase Sector Erase 2AAH 55H 555H AAH 555H 80H 2AAH 55H 555H AAH 555H 10H 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H Sector Address 30H ...

Page 18: ...3 Eon Silicon Solution Inc www essi com tw or modifications due to changes in technical specifications 18 EN29F040A Rev B Issue Date 2004 04 01 Flowchart 5 DATA Polling Algorithm No No DQ7 Data DQ5 1 DQ7 Data Yes Yes No Yes Read Data Start Read Data Fail Pass ...

Page 19: ... Eon Silicon Solution Inc www essi com tw or modifications due to changes in technical specifications 19 EN29F040A Rev B Issue Date 2004 04 01 Flowchart 6 Toggle Bit Algorithm No Yes DQ6 Toggle DQ5 1 DQ6 Toggle No No Yes Yes Read Data Start Read Data Fail Pass ...

Page 20: ...transitions A9 and OE may undershoot VSS to 1 0V for periods of up to 50 ns and to 2 0 V for periods of up to 20 ns See Left Figure Maximum DC input voltage on A9 and OE is 11 5 V which may overshoot to 12 5 V for periods up to 20 ns 3 No more than one output shorted to ground at a time Duration of the short circuit should not be greater than one second Stresses above those listed under Absolute M...

Page 21: ...A ICC1 Supply Current read TTL Byte CE VIL OE VIH f 6MHz 30 mA ICC2 Supply Current Standby TTL CE VIH 1 0 MA ICC3 Supply Current Standby CMOS CE Vcc 0 3V 5 0 µA ICC4 Supply Current Program or Erase Byte program Sector or Chip Erase in progress 30 mA VIL Input Low Voltage 0 5 0 8 V VIH Input High Voltage 2 Vcc 0 5 V VOL Output Low Voltage IOL 2 mA 0 45 V VOH Output High Voltage TTL IOH 2 5 mA 2 4 V...

Page 22: ...le To Output Delay OE VIL Max 45 55 70 90 ns tGLQV tOE Output Enable to Output Delay Max 25 30 30 35 ns tEHQZ tDF Chip Enable to Output High Z Max 10 15 20 20 ns tGHQZ tDF Output Enable to Output High Z Max 10 15 20 20 ns tAXQX tOH Output Hold Time from Addresses CE or OE whichever occurs first Min 0 0 0 0 ns Notes For 45 55 Vcc 5 0V 5 Output Load 1 TTL gate and 30pF Input Rise and Fall Times 5ns ...

Page 23: ... tDH Data Hold Time Min 0 0 0 0 ns tOES Output Enable Setup Time Min 0 0 0 0 ns Read MIn 0 0 0 0 ns tOEH Output Enable Hold Time Toggle and DATA Polling Min 10 10 10 10 ns tGHWL tGHWL Read Recovery Time before Write OE High to W E Low Min 0 0 0 0 ns tELWL tCS CE SetupTime Min 0 0 0 0 ns tWHEH tCH CE Hold Time Min 0 0 0 0 ns tWLWH tWP Write Pulse Width Min 25 30 35 45 ns tWHDL tWPH Write Pulse Widt...

Page 24: ... 30 45 ns tEHDX tDH Data Hold Time Min 0 0 0 0 ns tOES Output Enable Setup Time Min 0 0 0 0 ns Read 0 0 0 0 0 ns tOEH Output Enable Hold Time Toggle and Data Polling 10 10 10 10 10 ns tGHEL tGHEL Read Recovery Time before Write OE High to CE Low Min 0 0 0 0 ns tWLEL tWS W E SetupTime Min 0 0 0 0 ns tEHWH tWH W E Hold Time Min 0 0 0 0 ns tELEH tCP Write Pulse Width Min 25 30 35 45 ns tEHEL tCPH Wri...

Page 25: ... voltage with respect to Vss on all pins except I O pins including A9 and OE 1 0 V 12 0 V Input voltage with respect to Vss on all I O Pins 1 0 V Vcc 1 0 V Vcc Current 100 mA 100 mA Note These are latch up characteristics and the device should never be put under these conditions Refer to Absolute Maximum ratings for the actual operating limits Table 13 32 PIN PLCC PIN CAPACITANCE 25 C 1 0MHz Param...

Page 26: ...on Solution Inc www essi com tw or modifications due to changes in technical specifications 26 EN29F040A Rev B Issue Date 2004 04 01 Table 15 DATA RETENTION Parameter Description Test Conditions Min Unit 150 C 10 Years Minimum Pattern Data Retention Time 125 C 20 Years ...

Page 27: ... www essi com tw or modifications due to changes in technical specifications 27 EN29F040A Rev B Issue Date 2004 04 01 SWITCHING WAVEFORMS Figure 5 AC Waveforms for READ Operations Figure 6 AC Waveforms for Chip Sector Erase Operations Notes 1 SA is the Sector address for Sector erase ...

Page 28: ...ssue Date 2004 04 01 SWITCHING WAVEFORMS continued Figure 7 Program Operation Timings Notes 1 PA is address of the memory location to be programmed 2 PD is data to be programmed at byte address 3 DQ7 is the output of the complement of the data written to the device 4 DOUT is the output of data written to the device 5 Figure indicates last two bus cycles of four bus cycle sequence ...

Page 29: ...specifications 29 EN29F040A Rev B Issue Date 2004 04 01 Figure 8 AC Waveforms for DATA Polling During Embedded Algorithm Operations Notes DQ7 Valid Data The device has completed the embedded operation Figure 9 AC Waveforms for Toggle Bit During Embedded Algorithm Operations Notes DQ6 stops toggling The device has completed the embedded operation ...

Page 30: ...04 04 01 SWITCHING WAVEFORMS continued Figure 10 Alternate CE Controlled Write Operation Timings Notes 1 PA is address of the memory location to be programmed 2 PD is data to be programmed at byte address 3 DQ7 is the output of the complement of the data written to the device 4 DOUT is the output of data written to the device 5 Figure indicates last two bus cycles of four bus cycle sequence ...

Page 31: ...040A Rev B Issue Date 2004 04 01 ORDERING INFORMATION EN29F040A 45 P C P PACKAGING CONTENT Blank Conventional P Pb free TEMPERATURE RANGE C Commercial 0 C to 70 C I Industrial 40 C to 85 C PACKAGE P 32 Plastic DIP J 32 Plastic PLCC T 32 Plastic TSOP SPEED 45 45ns 55 55ns 70 70ns 90 90ns BASE PART NUMBER EN EON Silicon Solution Inc 29F FLASH 5V 040 512K x 8 A version A ...

Page 32: ... by subsequent versions 2003 Eon Silicon Solution Inc www essi com tw or modifications due to changes in technical specifications 32 EN29F040A Rev B Issue Date 2004 04 01 PHYSICAL DIMENSIONS PL 032 32 Pin Plastic Leaded Chip Carrier ...

Page 33: ...sed by subsequent versions 2003 Eon Silicon Solution Inc www essi com tw or modifications due to changes in technical specifications 33 EN29F040A Rev B Issue Date 2004 04 01 PHYSICAL DIMENSIONS continued PD 032 32 Pin Plastic DIP ...

Page 34: ...by subsequent versions 2003 Eon Silicon Solution Inc www essi com tw or modifications due to changes in technical specifications 34 EN29F040A Rev B Issue Date 2004 04 01 PHYSICAL DIMENSIONS continued TS 032 32 Pin Standard Thin Small ...

Page 35: ... www essi com tw or modifications due to changes in technical specifications 35 EN29F040A Rev B Issue Date 2004 04 01 Revisions List Revision No Description Date A Initial draft 2003 04 03 B Correct a typo of table 5 on page 8 Address bits A18 A16 uniquely select any Sector 2004 04 01 ...

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