This Data Sheet may be revised by subsequent versions ©2003 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
22
EN29F040A
Rev. B, Issue Date: 2004/04/01
Table 8. AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbols
Speed Options
JEDEC Standard
Description
Test Setup
-45 -55 -70 -90 Unit
t
AVAV
t
RC
Read Cycle Time
Min
45
55
70
90
ns
t
AVQV
t
ACC
Address to Output Delay
CE
= V
IL
OE
=
V
IL
Max
45
55 70 90 ns
t
ELQV
t
CE
Chip Enable To Output Delay
OE
=
V
IL
Max
45
55 70 90 ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
25
30
30
35
ns
t
EHQZ
t
DF
Chip Enable to Output High Z
Max
10
15
20
20
ns
t
GHQZ
t
DF
Output Enable to Output High Z
Max
10
15
20
20
ns
t
AXQX
t
OH
Output Hold Time from
Addresses,
CE
or
OE
,
whichever occurs first
Min
0
0
0
0
ns
Notes:
For -45, -55
Vcc = 5.0V ± 5%
Output Load : 1 TTL gate and 30pF
Input Rise and Fall Times: 5ns
Input Rise Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level, Input and Output: 1.5 V
For all others:
Vcc = 5.0V ± 10%
Output Load: 1 TTL gate and 100 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level, Input and Output: 0.8 V and 2.0 V
