LTC6804-1/LTC6804-2
33
680412fc
For more information
Figure 11. LTC6804 I
2
C/SPI Master Using GPIOs
680412 F11
COMM
REGISTER
GPIO
PORT
I
2
C/SPI
SLAVE
PORT A
RDCOMM
WRCOMM
STCOMM
LTC6804-1/LTC6804-2
operaTion
Any number of bytes can be transmitted to the slave in
groups of 3 bytes using these commands. The GPIO ports
will not get reset between different STCOMM commands.
However, if the wait time between the commands is greater
than 2 seconds, the watchdog will timeout and reset the
ports to their default values.
To transmit several bytes of data using an I
2
C master, a
START signal is only required at the beginning of the entire
data stream. A STOP signal is only required at the end of
the data stream. All intermediate data groups can use a
BLANK code before the data byte and an ACK/NACK signal
as appropriate after the data byte. SDA and SCL will not
get reset between different STCOMM commands.
To transmit several bytes of data using SPI master, a
CSBM low signal is sent at the beginning of the 1st data
byte. CSBM can be held low or taken high for intermediate
data groups using the appropriate code on FCOMn[3:0].
A CSBM high signal is sent at the end of the last byte of
data. CSBM, SDIOM and SCKM will not get reset between
different STCOMM commands.
Figure 12 shows the 24 clock cycles following STCOMM
command for an I
2
C master in different cases. Note that
if ICOMn[3:0] specified a STOP condition, after the STOP
signal is sent, the SDA and SCL lines are held high and
all data in the rest of the word is ignored. If ICOMn[3:0]
is a NO TRANSMIT, both SDA and SCL lines are released,
and rest of the data in the word is ignored. This is used
when a particular device in the stack does not have to
communicate to a slave.
Figure 13 shows the 24 clock cycles following STCOMM
command for a SPI master. Similar to the I
2
C master, if
ICOMn[3:0] specified a CSBM HIGH or a NO TRANSMIT
condition, the CSBM, SCKM and SDIOM lines of the SPI
master are released and the rest of the data in the word
is ignored.
RDCOMM Command:
The data received from the slave
device can be read back from the COMM register using the
RDCOMM command. The command reads back 6 bytes of
data followed by the PEC. See the section Bus Protocols
for more details on a read command format.
Table 18 describes the possible read back codes for
ICOMn[3:0] and FCOMn[3:0] when using the part as an I
2
C
master. Dn[7:0] contains the data byte either transmitted
by the I
2
C master or received from the I
2
C slave.
In case of the SPI master, the read back codes for
ICOMn[3:0] and FCOMn[3:0] are always 0111 and 1111
respectively. Dn[7:0] contains the data byte either trans-
mitted by the SPI master or received from the SPI slave.
Table 18. Read Codes for ICOMn[3:0] and FCOMn[3:0] on I
2
C
Master
CONTROL
BITS
CODE
DESCRIPTION
ICOMn[3:0]
0110
Master Generated a START Signal
0001
Master Generated a STOP Signal
0000
Blank, SDA Was Held Low Between Bytes
0111
Blank, SDA Was Held High Between Bytes
FCOMn[3:0]
0000
Master Generated an ACK Signal
0111
Slave Generated an ACK Signal
1111
Slave Generated a NACK Signal
0001
Slave Generated an ACK Signal, Master
Generated a STOP Signal
1001
Slave Generated a NACK Signal, Master
Generated a STOP Signal
Figure 11 illustrates the operation of LTC6804 as an I
2
C
or SPI master using the GPIOs.
