Linear Technology LTC6804-1, Manual

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LTC6804-1/LTC6804-2
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operaTion
Table 15. COMM Register Memory Map
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
COMM0 RD/WR ICOM0[3] ICOM0[2] ICOM0[1] ICOM0[0] D0[7] D0[6] D0[5] D0[4]
COMM1 RD/WR D0[3] D0[2] D0[1] D0[0] FCOM0[3] FCOM0[2] FCOM0[1] FCOM0[0]
COMM2 RD/WR ICOM1[3] ICOM1[2] ICOM1[1] ICOM1[0] D1[7] D1[6] D1[5] D1[4]
COMM3 RD/WR D1[3] D1[2] D1[1] D1[0] FCOM1[3] FCOM1[2] FCOM1[1] FCOM1[0]
COMM4 RD/WR ICOM2[3] ICOM2[2] ICOM2[1] ICOM2[0] D2[7] D2[6] D2[5] D2[4]
COMM5 RD/WR D2[3] D2[2] D2[1] D2[0] FCOM2[3] FCOM2[2] FCOM2[1] FCOM2[0]
Table 13
WATCHDOG TIMER SOFTWARE TIMER
SWTEN = 0, DCTO = XXXX Resets CFGR0-5
When It Activates
Disabled
SWTEN = 1, DCTO = 0000 Resets CFGR0-5
When It Activates
Disabled
SWTEN = 1, DCTO ! = 0000 Resets CFGR0-3
When It Activates
Resets CFGR4-5
When It Fires
Unlike the watchdog timer, the software timer does not
reset when there is a valid command. The software timer
can only be reset after a valid WRCFG (write configuration
register) command. There is a possibility that the software
timer will expire in the middle of some commands.
If software timer activates in the middle of WRCFG com-
mand, the configuration register resets as per Table 14.
However, at the end of the valid WRCFG command, the
new data is copied to the configuration register. The new
data is not lost when the software timer is activated.
If software timer activates in the middle of RDCFG com-
mand, the configuration register group resets as per
Table 14. As a result, the read back data from bytes CRFG4
and CRFG5 could be corrupted.
I
2
C/SPI MASTER ON LTC6804 USING GPIOS
The I/O ports GPIO3, GPIO4 and GPIO5 on LTC6804-1 and
LTC6804-2 can be used as an I
2
C or SPI master port to
communicate to an I
2
C or SPI slave. In the case of an I
2
C
master, GPIO4 and GPIO5 form the SDA and SCL ports of
the I
2
C interface respectively. In the case of a SPI master,
GPIO3, GPIO5 and GPIO4 become the chip select (CSBM),
clock (SCKM) and data (SDIOM) ports of the SPI interface
respectively. The SPI master on LTC6804 supports only
SPI mode 3 (CHPA = 1, CPOL = 1).
Table 14
DCTO
(READ VALUE) TIME LEFT (MIN)
0 Disabled (or) Timer Has Timed Out
1 0 < Timer ≤ 0.5
2 0.5 < Timer ≤ 1
3 1 < Timer ≤ 2
4 2 < Timer ≤ 3
5 3 < Timer ≤ 4
6 4 < Timer ≤ 5
7 5 < Timer ≤ 10
8 10 < Timer ≤ 15
9 15 < Timer ≤ 20
A 20 < Timer ≤ 30
B 30 < Timer ≤ 40
C 40 < Timer ≤ 60
D 60 < Timer ≤ 75
E 75 < Timer ≤ 90
F 90 < Timer ≤ 120
The GPIOs are open drain outputs, so an external pull-up
is required on these ports to operate as an I
2
C or SPI
master. It is also important to write the GPIO bits to 1 in
the CFG register group so these ports are not pulled low
internally by the device.
COMM Register
LTC6804 has a 6-byte COMM register as shown in Table 15.
This register stores all data and control bits required for
I
2
C or SPI communication to a slave. The COMM register
contains 3 bytes of data Dn[7:0] to be transmitted to or
received from the slave device. ICOMn [3:0] specify con-
trol actions before transmitting/receiving the data byte.
FCOMn [3:0] specify control actions after transmitting/
receiving the data byte.