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Transformer Selection Guide

As shown in Figure 41, a transformer or pair of transform-

ers isolates the isoSPI signals between two isoSPI ports.

The isoSPI signals have programmable pulse amplitudes

up to 1.6V

P-P

and pulse widths of 50ns and 150ns. To be

able to transmit these pulses with the necessary fidelity

the system requires that the transformers have primary

inductances above 60µH and a 1:1 turns ratio. It is also

necessary to use a transformer with less than 2.5µH of

leakage inductance. In terms of pulse shape the primary

inductance will mostly effect the pulse droop of the 50ns

and 150ns pulses. If the primary inductance is too low,

the pulse amplitude will begin to droop and decay over

the pulse period. When the pulse droop is severe enough,

the effective pulse width seen by the receiver will drop

substantially, reducing noise margin. Some droop is ac-

ceptable as long as it is a relatively small percentage of

applicaTions inForMaTion

the total pulse amplitude. The leakage inductance primarily

affects the rise and fall times of the pulses. Slower rise

and fall times will effectively reduce the pulse width. Pulse

width is determined by the receiver as the time the signal

is above the threshold set at the ICMP pin. Slow rise and

fall times cut into the timing margins. Generally it is best

to keep pulse edges as fast as possible. When evaluating

transformers, it is also worth noting the parallel winding

capacitance. While transformers have very good CMRR at

low frequency, this rejection will degrade at higher frequen-

cies, largely due to the winding to winding capacitance.

When choosing a transformer, it is best to pick one with

less parallel winding capacitance when possible.
When choosing a transformer, it is equally important to

pick a part that has an adequate isolation rating for the

application. The working voltage rating of a transformer

is a key spec when selecting a part for an application.

Table 48. Recommended Transformers

MANUFACTURER

PART NUMBER

TEMPERATURE

RANGE

WORKING

HIPOT

/60s CT CMC

(W/LEADS) PINS

AEC–

q200

Dual Transformers

Pulse

HX1188FNL

–40°C to 85°C

60V (est)

1.5kVrms

6.0mm 12.7mm

9.7mm

16SMT

–

Pulse

HX0068ANL

–40°C to 85°C

60V (est)

1.5kVrms

2.1mm 12.7mm

9.7mm

16SMT

–

Pulse

HM2100NL

–40°C to 105°C

1000V

4.3kVdc

–

3.4mm 14.7mm

14.9mm

10SMT

Pulse

HM2102NL

–40°C to 125°C

1000V

4.3kVdc

4.9mm 14.8mm

14.7mm

12SMT

Sumida

CLP178–C20114

–40°C to 125°C 1000V (est) 3.75kVrms

9mm

17.5mm

15.1mm

12SMT

–

Sumida

CLP0612–C20115

600Vrms 3.75kVrms

–

5.7mm 12.7mm

9.4mm

16SMT

–

Wurth Elektronik

7490140110

–40°C to 85°C

250Vrms

4kVrms

10.9mm 24.6mm

17.0mm

16SMT

–

Wurth Elektronik

7490140111

0°C to 70°C

1000V (est) 4.5kVrms

–

8.4mm 17.1mm

15.2mm

12SMT

–

Wurth Elektronik

749014018

0°C to 70°C

250Vrms

4kVrms

8.4mm 17.1mm

15.2mm

12SMT

–

Halo

TG110–AE050N5LF

–40°C to 85/125°C 60V (est)

1.5kVrms

6.4mm 12.7mm

9.5mm

16SMT

Single Transformers

Pulse

PE–68386NL

–40°C to 130°C

60V (est)

1.5kVdc

–

2.5mm

6.7mm

8.6mm

6SMT

–

Pulse

HM2101NL

–40°C to 105°C

1000V

4.3kVdc

–

5.7mm

7.6mm

9.3mm

6SMT

Wurth Elektronik

750340848

–40°C to 105°C

250V

3kVrms

–

2.2mm

4.4mm

9.1mm

4SMT

–

Halo

TGR04–6506V6LF

–40°C to 125°C

300V

3kVrms

–

10mm

9.5mm

12.1mm

6SMT

–

Halo

TGR04–A6506NA6NL

–40°C to 125°C

300V

3kVrms

–

9.4mm

8.9mm

12.1mm

6SMT

TDK

ALT4532V–201–T001

–40°C to 105°C

60V (est)

~1kV

–

2.9mm

3.2mm

4.5mm

6SMT

Halo

TDR04–A550ALLF

–40°C to 105°C

1000V

5kVrms

–

6.4mm

8.9mm

16.6mm

6TH

Sumida

CEEH96BNP–LTC6804/11 –40°C to 125°C

600V

2.5kVrms

–

7mm

9.2mm

12.0mm

4SMT

–

Sumida

CEP99NP–LTC6804

–40°C to 125°C

600V

2.5kVrms

–

10mm

9.2mm

12.0mm

8SMT

–

Sumida

ESMIT–4180/A

–40°C to 105°C

250Vrms

3kVrms

–

3.5mm

5.2mm

9.1mm

4SMT

TDK

VGT10/9EE–204S2P4

–40°C to 125°C

250V (est) 2.8kVrms

–

10.6mm 10.4mm

12.7mm

8SMT

–

Summary of Contents for LTC6804-1

Page 1: ...inear Technology and the Linear logo are registered and isoSPI is a trademark of Linear Technology Corporation All other trademarks are the property of their respective owners Protected by U S patents including 8908799 9182428 9270133 Total Measurement Error vs Temperature of 5 Typical Units Applications n n Measures Up to 12 Battery Cells in Series n n Stackable Architecture Supports 100s of Cell...

Page 2: ...I Physical Layer 36 2 Wire Isolated Interface isoSPI Physical Layer 36 Data Link Layer 44 Network Layer 44 Programming Examples 54 Simple Linear Regulator 58 Improved Regulator Power Efficiency 58 Fully Isolated Power 59 Reading External Temperature Probes 59 Expanding the Number of Auxiliary Measurements 60 Internal Protection Features 60 Filtering of Cell and GPIO Inputs 60 Cell Balancing with I...

Page 3: ...16 17 18 19 20 21 22 23 24 TOP VIEW G PACKAGE 48 LEAD PLASTIC SSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 V C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 IPB IMB ICMP IBIAS SDO NC SDI NC SCK IPA CSB IMA ISOMD WDT DRIVE VREG SWTEN VREF1 VREF2 GPIO5 GPIO4 V V GPIO3 GPIO2 GPIO1 C0 S1 TJMAX 150 C θJA 55 C W THE FUNCTION OF THESE PINS DEPEND...

Page 4: ...mperature range otherwise specifications are at TA 25 C The test conditions are V 39 6V VREG 5 0V unless otherwise noted TUBE TAPE AND REEL PART MARKING PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6804IG 1 PBF LTC6804IG 1 TRPBF LTC6804G 1 48 Lead Plastic SSOP 40 C to 85 C LTC6804HG 1 PBF LTC6804HG 1 TRPBF LTC6804G 1 48 Lead Plastic SSOP 40 C to 125 C LTC6804IG 2 PBF LTC6804IG 2 TRPBF LTC680...

Page 5: ...ode C n to C n 1 GPIO n to V 0 2 mV C n to C n 1 GPIO n to V 2 0 l 4 mV C n to C n 1 GPIO n to V 3 3 l 4 7 mV C n to C n 1 GPIO n to V 4 2 l 8 3 mV C n to C n 1 GPIO n to V 5 0 10 mV Sum of Cells V CO V l 0 3 1 Internal Temperature T Maximum Specified Temperature 5 C VREG Pin l 0 3 1 VREF2 Pin l 0 1 0 25 Digital Supply Voltage VREGD l 0 2 2 Input Range C n n 1 to 12 l C n 1 C n 1 5 V C0 l 0 GPIO n...

Page 6: ...e Core REFUP or MEASURE 0 4 0 55 0 7 mA l 0 375 0 55 0 725 mA IREG CORE VREG Supply Current See Figure 1 LTC6804 Operation State diagram State Core SLEEP isoSPI IDLE VREG 5V 2 2 4 µA VREG 5V l 2 2 6 µA State Core STANDBY 10 35 60 µA l 6 35 65 µA State Core REFUP 0 2 0 45 0 7 mA l 0 15 0 45 0 75 mA State Core MEASURE 10 8 11 5 12 2 mA l 10 7 11 5 12 3 mA IREG isoSPI Additional VREG Supply Current i...

Page 7: ... REFUP State in Fast Mode Measure 12 Cells l 1010 1113 1185 µs Measure 2 Cells l 180 201 215 µs Measure 12 Cells and 2 GPIO Inputs l 1420 1564 1660 µs tSKEW1 Figure 6 Skew Time The Time Difference between C12 and GPIO2 Measurements Command ADCVAX Fast Mode l 189 208 221 µs Normal Mode l 493 543 576 µs tSKEW2 Figure 3 Skew Time The Time Difference between C12 and C0 Measurements Command ADCV Fast M...

Page 8: ... VICMP 3 167mV V RIN Receiver Input Resistance Single Ended to IPA IMA IPB IMB l 27 35 43 kΩ isoSPI Idle Wakeup Specifications See Figure 21 VWAKE Differential Wake Up Voltage tDWELL 240ns l 200 mV tDWELL Dwell Time at VWAKE Before Wake Detection VWAKE 200mV l 240 ns tREADY Startup Time After Wake Detection l 10 µs tIDLE Idle Timeout Duration l 4 3 5 5 6 7 ms isoSPI Pulse Timing Specifications See...

Page 9: ... ADC specifications are guaranteed by the Total Measurement Error specification Note 3 The ACTIVE state current is calculated from DC measurements The ACTIVE state current is the additional average supply current into VREG when there is continuous 1MHz communications on the isoSPI ports with 50 data 1 s and 50 data 0 s Slower clock rates reduce the supply current See Applications Information secti...

Page 10: ...S CHANGE IN GAIN ERROR ppm 125 NUMBER OF PARTS 20 25 30 25 50 75 50 25 0 680412 G02 15 10 100 75 5 0 35 260 C 1 CYCLE TIME HOURS 0 MEASUREMENT ERROR ppm 30 5 25 15 20 10 0 680412 G03 3000 1000 2000 2500 500 1500 CELL VOLTAGE 3 3V 8 TYPICAL PARTS INPUT V 0 MEASUREMENT ERROR mV 0 5 0 0 5 3 5 680412 G04 1 0 1 5 2 0 1 2 4 1 0 1 5 2 0 10 ADC MEASUREMENTS AVERAGED AT EACH INPUT INPUT V 0 MEASUREMENT ERR...

Page 11: ...4 8 5 0 5 2 1 5 2 0 1 5 VIN 2V VIN 3 3V VIN 4 2V FREQUENCY Hz 100 PSRR dB 60 50 40 1M 680412 G14 70 80 65 55 45 75 85 90 1k 10k 100k 10M V DC 39 6V V AC 5VP P 1 BIT CHANGE 90dB VREG GENERATED FROM DRIVE PIN FIGURE 28 FREQUENCY Hz 100 20 10 0 1M 68412 G15 30 40 1k 10k 100k 10M 50 60 70 PSRR dB VREG DC 5V VREG AC 500mVP P 1 BIT CHANGE 70dB Cell Measurement Error vs Input RC Values GPIO Measurement E...

Page 12: ...2 3 6 5 35 65 75 125 C 85 C 25 C 45 C SLEEP SUPPLY CURRENT V CURRENT VREG CURRENT V V 15 5 40 STANDBY SUPPLY CURRENT µA 50 80 25 45 55 680412 G23 70 60 35 65 75 125 C 85 C 25 C 45 C STANDBY SUPPLY CURRENT V CURRENT VREG CURRENT V V 15 5 850 REFUP SUPPLY CURRENT µA 1000 25 45 55 680412 G24 950 900 35 65 75 125 C 85 C 25 C 45 C REFUP SUPPLY CURRENT V CURRENT VREG CURRENT Measure Mode Supply Current ...

Page 13: ... V V 5 CHANGE IN V REF2 ppm 150 35 580412 G30 0 100 15 25 45 150 200 200 100 50 50 55 65 75 125 C 85 C 25 C 45 C VREG GENERATED FROM DRIVE PIN FIGURE 28 VREG V 4 5 150 CHANGE IN V REF2 ppm 100 50 0 50 100 150 RL 5k 4 75 5 5 25 5 5 680412 G31 125 C 85 C 25 C 45 C V REF2 V CSB 1 5 2 5 3 5 680412 G32 0 5 5 1 0 2 0 3 0 0 0 5 1ms DIV VREF2 CSB RL 5k CL 1µF TIME HOURS 0 CHANGE IN V REF2 ppm 0 680412 G33...

Page 14: ...0 1 0 20 125 C 85 C 25 C 45 C V 39 6V V V 5 15 15 CHANGE IN DRIVE PIN VOLTAGE mV 5 10 25 45 55 680412 G39 10 5 0 35 65 75 125 C 85 C 25 C 45 C 4 5 6 680412 G40 3 2 100µs DIV 1 0 1 V DRIVE AND V REG V VDRIVE VREG VREG CL 1µF VREG GENERATED FROM DRIVE PIN FIGURE 28 V REF1 V CSB 1 5 2 5 3 5 680412 G41 0 5 5 5 1 0 2 0 3 0 CSB 0 1ms DIV VREF1 CL 1µF TEMPERATURE C 50 3 145 V REF1 V 3 146 3 148 3 149 3 1...

Page 15: ... 1mA 3 PARTS BIAS CURRENT µA 0 IBIAS PIN VOLTAGE V 2 000 2 005 800 408912 G47 1 995 1 990 200 400 600 1000 2 010 BIAS CURRENT µA 0 CURRENT GAIN mA mA 21 22 23 800 680412 G48 20 19 18 200 400 600 1000 VA 0 5V VA 1 0V VA 1 6V TEMPERATURE C 50 25 18 CURRENT GAIN mA mA 20 23 0 50 75 680412 G49 19 22 21 25 100 125 IB 100µA IB 1mA PULSE AMPLITUDE V 0 2 5 DRIVER COMMON MODE V 3 0 3 5 4 0 4 5 5 0 5 5 0 5 ...

Page 16: ... 1 Data Read Back from a Daisy Chained Device ISOMD 1 CSB 5V DIV SDI 5V DIV SCK 5V DIV SDO 5V DIV IPB IMB 2V DIV PORT B 1µs DIV 680412 G54 ISOMD V BEGINNING OF A COMMAND PORT A IPB IMB 1V DIV PORT B IPA IMA 1V DIV PORT A 1µs DIV 680412 G55 ISOMD VREG BEGINNING OF A COMMAND CSB 5V DIV SDI 5V DIV SCK 5V DIV SDO 5V DIV IPB IMB 2V DIV PORT B PORT A 1µs DIV 680412 G56 ISOMD V END OF A READ COMMAND IPB ...

Page 17: ...upsignal seeFigure21 within2seconds the watchdog timer circuit will reset the LTC6804 and the WDT pin will go high impedance Serial Port Pins LTC6804 1 DAISY CHAINABLE LTC6804 2 ADDRESSABLE ISOMD VREG ISOMD V ISOMD VREG ISOMD V PORT B Pins 45 to 48 IPB IPB A3 A3 IMB IMB A2 A2 ICMP ICMP A1 A1 IBIAS IBIAS A0 A0 PORT A Pins 41 to 44 NC SDO IBIAS SDO NC SDI ICMP SDI IPA SCK IPA SCK IMA CSB IMA CSB CSB...

Page 18: ... M S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 LOGIC AND MEMORY DIGITAL FILTERS SERIAL I O PORT B 6 CELL MUX VREGD SOC VREG P M AUX MUX 12 BALANCE FETs S n C n 1 P M 6 CELL MUX POR VREGD VREG SERIAL I O PORT A SOFTWARE TIMER DIE TEMPERATURE 2ND REFERENCE 1ST REFERENCE REGULATORS ADC2 ADC1 16 16 V LDO1 VREGD POR V LDO2 DRIVE 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 3...

Page 19: ...S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 LOGIC AND MEMORY DIGITAL FILTERS SERIAL I O ADDRESS 6 CELL MUX VREGD SOC VREG P M AUX MUX P M 6 CELL MUX POR VREGD VREG SERIAL I O PORT A SOFTWARE TIMER DIE TEMPERATURE 2ND REFERENCE 1ST REFERENCE REGULATORS ADC2 ADC1 V LDO1 VREGD POR V LDO2 DRIVE VREG VREF1 VREF2 V V V 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8...

Page 20: ...scharge timer is disabled only the watchdog timer is relevant REFUP State ToreachthisstatetheREFONbitintheConfigurationReg ister Group must be set to 1 using the WRCFG command see Table 36 The ADCs are off The reference is powered upsothattheLTC6804caninitiateADCconversionsmore quickly than from the STANDBY state When a valid ADC command is received the IC goes to the MEASURE state to begin the co...

Page 21: ...ut requires 5V and provides power to the remaining core circuitry and the isoSPI circuitry The VREG input can be powered through an external transistor driven by the regulated DRIVE output pin Alternatively VREG can be powered by an external supply The power consumption varies according to the opera tional states Table 1 and Table 2 provide equations to approximate the supply pin currents in each ...

Page 22: ... fast mode The increase in speed comes from a reduction in the oversampling ratio This results in an increase in noise and average measurement error Mode 26Hz Filtered In this mode the ADC digital filter 3dB frequency is lowered to 26Hz by increasing the OSR This mode is also referred to as the filtered mode due to its low 3dB frequency The accuracy is similar to the 7kHz Normal mode with lower no...

Page 23: ... see Figure 2 Table 4 summarizes the total noise in this range for all six ADC operating modes Also shown is the noise free resolution For example 14 bit noise free resolution in normal mode implies that the top 14 bits will be noise free with a DC input but that the 15th and 16th least significant bits LSB will flicker ADC Range vs Voltage Reference Value Typical Delta Sigma ADC s have a range wh...

Page 24: ...eration Figure 3 Timing for ADCV Command Measuring All 12 Cells Table 6 Conversion Times for ADCV Command Measuring Only 2 Cells in Different Modes CONVERSION TIMES in µs MODE t0 t1M t1C 27kHz 0 57 201 14kHz 0 86 230 7kHz 0 144 405 3kHz 0 260 521 2kHz 0 493 754 26Hz 0 29 817 33 568 Table 5 Conversion Times for ADCV Command Measuring All 12 Cells in Different Modes CONVERSION TIMES in µs MODE t0 t1...

Page 25: ...xiliary GPIO Measurements ADAX Command The ADAX command initiates the measurement of the GPIO inputs This command has options to select which GPIO input to measure GPIO1 5 and which ADC mode The ADAX command also measures the 2nd reference There are options in the ADAX command to measure each GPIO and the 2nd reference separately or to measure all 5 GPIOsandthe2ndreferenceinasinglecommand Seethe s...

Page 26: ...mmand is a diagnostic command that measures the following internal device parameters sum of all cells SOC internal die temperature ITMP analog power supply VA and the digital power supply VD These parameters are described in the section below All 6 ADC modes are available for these conversions See the section on commands for the ADSTAT command format Figure 7 illustrates the timing of the ADSTAT c...

Page 27: ...e of the digital power supply measurement VD is stored in status register group B From VA and VD the power supply measurements are given by Analogpowersupplymeasurement VREG VA 100µV Digital power supply measurement VREGD VD 100µV The nominal range of VREG is 4 5V to 5 5V The nominal range of VREGD is 2 7V to 3 6V Issuing an ADSTAT command with CHST 100 runs an ADC measurement of just the digital ...

Page 28: ...x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA AXST ST 1 0 01 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 G1V to G5V REF AUXA AUXB ST 1 0 10 0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA STATST ST 1 0 01 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 SOC ITMP VA VD STATA STATB ST 1 0 10 0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA Figure 8 Operation of LTC6804 ADC Self Test 680412 F08 RESULTS REGISTER DIGITAL FILTER ...

Page 29: ...d and store them in array CELLPU n 2 Run the 12 cell command ADOW with PUP 0 at least twice Readthecellvoltagesforcells1through12once at the end and store them in array CELLPD n 3 Take the difference between the pull up and pull down measurements made in above steps for cells 2 12 CELL n CELLPU n CELLPD n 4 For all values of n from 1 to 11 If CELL n 1 400mV then C n is open If the CELLPU 1 0 0000 ...

Page 30: ...the watchdog timer expires This resets configuration register bytes CFGR0 CFGR3 in all cases CFGR4 and CFGR5 are reset by the watchdog timer when the software timer is disabled The WDT pin is pulled high by the external pull up when the watchdog time elapses The watchdog timer is always enabled and is reset by a qualified wake up signal Thesoftwaredischargetimerisusedtokeepthedischarge switches tu...

Page 31: ... middle of RDCFG com mand the configuration register group resets as per Table 14 As a result the read back data from bytes CRFG4 and CRFG5 could be corrupted I2C SPI Master on LTC6804 Using GPIOS TheI OportsGPIO3 GPIO4andGPIO5onLTC6804 1and LTC6804 2 can be used as an I2C or SPI master port to communicate to an I2C or SPI slave In the case of an I2C master GPIO4 and GPIO5 form the SDA and SCL por...

Page 32: ... 0 and FCOMn 3 0 and their behavior when using the part as a SPI master Note that only the codes listed in Tables 16 and 17 are valid for ICOMn 3 0 and FCOMn 3 0 Writing any other code that is not listed in Tables 16 and 17 to ICOMn 3 0 and FCOMn 3 0 may result in unexpected behavior on the I2C and SPI ports COMM Commands ThreecommandshelpaccomplishI2CorSPIcommunica tion to the slave device WRCOMM...

Page 33: ...If ICOMn 3 0 is a NO TRANSMIT both SDA and SCL lines are released and rest of the data in the word is ignored This is used when a particular device in the stack does not have to communicate to a slave Figure 13 shows the 24 clock cycles following STCOMM command for a SPI master Similar to the I2C master if ICOMn 3 0 specified a CSBM HIGH or a NO TRANSMIT condition the CSBM SCKM and SDIOM lines of ...

Page 34: ... NO TRANSMIT CSBM GPIO3 SDIOM GPIO4 SCKM GPIO5 CSBM GPIO3 CSBM LOW CSBM LOW HIGH SDIOM GPIO4 SCKM GPIO5 CSBM GPIO3 CSBM HIGH LOW CSBM LOW SCK tCLK t4 t3 Figure 12 STCOMM Timing Diagram for an I2C Master SDA GPIO4 680412 F12 SCL GPIO5 NO TRANSMIT SDA GPIO4 SCL GPIO5 STOP SDA GPIO4 SCL GPIO5 START ACK SDA GPIO4 SCL GPIO5 START NACK STOP SDA GPIO4 SCL GPIO5 BLANK NACK SCK tCLK t4 t3 ...

Page 35: ...ng t3 Min 200ns CSBM Falling to SCKM Rising tCLK t3 Min 1 2µs SCKM Falling to SDIOM Valid Master requires tCLK Note When using isoSPI t4 is generated internally and is a minimum of 30ns Also t3 tCLK t4 When using SPI t3 and t4 are the low and high times of the SCK input each with a specified minimum of 200ns Timing Specifications of I2C and SPI master The timing of the LTC6804 I2C or SPI master wi...

Page 36: ...erial Port A for 4 wire SPI The SDO pin is an open drain output which requires a pull up resistor tied to the appropriate supply voltage Figure 14 Timing The 4 wire serial port is configured to operate in a SPI system using CPHA 1 and CPOL 1 Consequently data on SDI must be stable during the rising edge of SCK The timing is depicted in Figure 15 The maximum data rate is 1Mbps 2 Wire Isolated Inter...

Page 37: ... resistor RM in parallel with the characteristic impedance of the cable External Connections The LTC6804 1 has 2 serial ports which are called Port B andPortA PortBisalwaysconfiguredasa2 wireinterface master The final device in the daisy chain does not use this port and it should be terminated into RM Port A is either a 2 wire or 4 wire interface slave depending on the connection of the ISOMD pin ...

Page 38: ...arator volt age threshold are set by a resistor divider RBIAS RB1 RB2 between the IBIAS and V The divided voltage is connected to the ICMP pin which sets the comparator threshold to 1 2 of this voltage VICMP When either isoSPI interface is enabled not IDLE IBIAS is held at 2V causing a current IB to flow out of the IBIAS pin The IP and IM pin drive currents are 20 IB As an example if divider resis...

Page 39: ...VDDS EN MISO MOSI SCK CS VDD POL PHA MSTR ICMP IBIAS GND SLOW IP IM MISO MOSI CLK CS V DD MPU LTC6820 680412 F17 VDDS EN MISO MOSI SCK CS VDD POL PHA MSTR ICMP IBIAS GND SLOW IP IM MISO MOSI CLK CS V DD MPU LTC6820 V C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 IPB IMB ICMP IBIAS SDO NC SDI NC SCK IPA CSB IMA ISOMD WDT DRIVE V REG SWTEN V REF1 V REF2 GPIO5 GPIO4 V V G...

Page 40: ...MISO MOSI SCK CS VDD POL PHA MSTR ICMP IBIAS GND SLOW IP IM MISO MOSI CLK CS VDD MPU LTC6820 V C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 A3 A2 A1 A0 SDO IBIAS SDI ICMP SCK IPA CSB IMA ISOMD WDT DRIVE VREG SWTEN VREF1 VREF2 GPIO5 GPIO4 V V GPIO3 GPIO2 GPIO1 C0 S1 LTC6804 2 ADDRESS 0 0 680412 F18c V C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2...

Page 41: ...on through the LTC6804 1 daisy chain Long pulses are used to transmit CSB changes and short pulses are used to transmit data as explained in Table 22 Table 22 LTC6804 1 Port B Master isoSPI Port Function COMMUNICATION EVENT PORT A SPI TRANSMITTED PULSE PORT B isoSPI CSB Rising Long 1 CSB Falling Long 1 SCK Rising Edge SDI 1 Short 1 SCK Rising Edge SDI 0 Short 1 On the other side of the isolation b...

Page 42: ...ISO A3 is the same signal but with the cable delay shown between parts 2 and 3 Bits Wn W0 refers to the 16 bit command code and the 16 bit PEC of a READ command At the end of bit W0 the 3 parts decode the READ command and begin shifting out data which is valid on the next rising edge of clock SCK BitsXn X0 refertothedatashiftedoutbyPart1 BitsYn Y0 refer to the data shifted out by Part 2 and bits Z...

Page 43: ...tate Method 1 can be used when all devices on the daisy chain are in the IDLE state This guarantees that they propagate the wake up signal up the daisy chain However this method will fail to wake up all devices when a device in the middle of the chain is in the READY state instead of IDLE When this happens the device in READY state will not propagate the wake up pulse so the devices above it will ...

Page 44: ...0000000010000 PEC is a 15 bit register group 2 For each bit DIN coming into the PEC register group set IN0 DIN XOR PEC 14 IN3 IN0 XOR PEC 2 IN4 IN0 XOR PEC 3 IN7 IN0 XOR PEC 6 IN8 IN0 XOR PEC 7 IN10 IN0 XOR PEC 9 IN14 IN0 XOR PEC 13 3 Update the 15 bit PEC as follows PEC 14 IN14 PEC 13 PEC 12 PEC 12 PEC 11 PEC 11 PEC 10 PEC 10 IN10 PEC 9 PEC 8 PEC 8 IN8 PEC 7 IN7 PEC 6 PEC 5 PEC 5 PEC 4 PEC 4 IN4 ...

Page 45: ...6 Operation LTC6804calculatesPECforanycommandordatareceived and compares it with the PEC following the command or data The command or data is regarded as valid only if the PEC matches LTC6804 also attaches the calculated PEC at the end of the data it shifts out Table 25 shows the format of PEC while writing to or reading from LTC6804 While writing any command to LTC6804 the command bytes CMD0 and ...

Page 46: ...her serial communication while waiting for ADC conversions to complete The next method overcomes this limitation The controller cansendanADCstartcommand performothertasks and then send a poll ADC converter status PLADC command todeterminethestatusoftheADCconversions Figure24 After entering the PLADC command SDO will go low if the device is busy performing conversions SDO is pulled high at the end ...

Page 47: ... still busy performing conversions and does not return a pulse if it has completed conversions If a CSB high isoSPI pulse is sent to the LTC6804 2 it exits thepollingcommand Notethatbroadcastpollcommands are not compatible with parallel isoSPI Bus Protocols Protocol Format The protocol formats for both broadcast and address commands are depicted in Table 27 through Table 31 Table 26 is the key for...

Page 48: ...9 CC 8 CMD1 WR CC 7 CC 6 CC 5 CC 4 CC 3 CC 2 CC 1 CC 0 Table 33 Address Command Format NAME RD WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CMD0 WR 1 a3 a2 a1 a0 CC 10 CC 9 CC 8 CMD1 WR CC 7 CC 6 CC 5 CC 4 CC 3 CC 2 CC 1 CC 0 ax is Address Bit x Command Format The formats for the broadcast and address commands are shown in Table 32 and Table 33 respectively The 11 bit command code CC 10 0 is...

Page 49: ...C Con version and Poll Status ADOW 0 1 MD 1 MD 0 PUP 1 DCP 1 CH 2 CH 1 CH 0 Start Self Test Cell Voltage Conversion and Poll Status CVST 0 1 MD 1 MD 0 ST 1 ST 0 0 0 1 1 1 Start GPIOs ADC Conversion and Poll Status ADAX 1 0 MD 1 MD 0 1 1 0 0 CHG 2 CHG 1 CHG 0 Start Self Test GPIOs Conversion and Poll Status AXST 1 0 MD 1 MD 0 ST 1 ST 0 0 0 1 1 1 Start Status group ADC Conversion and Poll Status ADS...

Page 50: ...st Mode Selection Self Test Conversion Result ST 27kHz 14kHz 7kHz 3kHz 2kHz 26Hz 01 Self Test 1 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 10 Self test 2 0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA CHG 2 0 GPIO Selection for ADC Conversion Total Conversion Time in the 6 ADC Modes CHG 27kHz 14kHz 7kHz 3kHz 2kHz 26Hz 000 GPIO 1 5 2nd Ref 1 1ms 1 3ms 2 3ms 3 0ms 4 4ms 201ms 001 GPIO 1 201µs 230µs 405µs ...

Page 51: ... C4V 7 C4V 6 C4V 5 C4V 4 C4V 3 C4V 2 C4V 1 C4V 0 CVBR1 RD C4V 15 C4V 14 C4V 13 C4V 12 C4V 11 C4V 10 C4V 9 C4V 8 CVBR2 RD C5V 7 C5V 6 C5V 5 C5V 4 C5V 3 C5V 2 C5V 1 C5V 0 CVBR3 RD C5V 15 C5V 14 C5V 13 C5V 12 C5V 11 C5V 10 C5V 9 C5V 8 CVBR4 RD C6V 7 C6V 6 C6V 5 C6V 4 C6V 3 C6V 2 C6V 1 C6V 0 CVBR5 RD C6V 15 C6V 14 C6V 13 C6V 12 C6V 11 C6V 10 C6V 9 C6V 8 Table 39 Cell Voltage Register Group C REGISTER ...

Page 52: ...3 BIT 2 BIT 1 BIT 0 STAR0 RD SOC 7 SOC 6 SOC 5 SOC 4 SOC 3 SOC 2 SOC 1 SOC 0 STAR1 RD SOC 15 SOC 14 SOC 13 SOC 12 SOC 11 SOC 10 SOC 9 SOC 8 STAR2 RD ITMP 7 ITMP 6 ITMP 5 ITMP 4 ITMP 3 ITMP 2 ITMP 1 ITMP 0 STAR3 RD ITMP 15 ITMP 14 ITMP 13 ITMP 12 ITMP 11 ITMP 10 ITMP 9 ITMP 8 STAR4 RD VA 7 VA 6 VA 5 VA 4 VA 3 VA 2 VA 1 VA 0 STAR5 RD VA 15 VA 14 VA 13 VA 12 VA 11 VA 10 VA 9 VA 8 Table 44 Status Regi...

Page 53: ... x Voltage x 1 to 12 16 Bit ADC Measurement Value for Cell x Cell Voltage for Cell x CxV 100µV CxV Is Reset to 0xFFFF on Power Up and After Clear Command GxV GPIO x Voltage x 1 to 5 16 Bit ADC Measurement Value for GPIOx Voltage for GPIOx GxV 100µV GxV Is Reset to 0xFFFF on Power Up and After Clear Command REF 2nd Reference Voltage 16 Bit ADC Measurement Value for 2nd Reference Voltage for 2nd Ref...

Page 54: ...egisters 0 to 4095 for 12 bits and 0 to 65535 for 16 bits Programming Examples The following examples use a configuration of 3 stacked LTC6804 1 devices S1 S2 S3 Port A on device S1 is configured in SPI mode ISOMD pin low Port A on de vices S2 and S3 is configured in isoSPI mode ISOMD pin high Port B on S1 is connected to Port A on S2 Port B on S2 is connected to Port A on S3 The microcontroller c...

Page 55: ...de with discharge permitted and poll status 1 Pull CSB low 2 Send ADCV command with MD 1 0 10 and DCP 1 i e 0x03 0x70 and its PEC 0xAF 0x42 3 Pull CSB high Clear Cell Voltage Registers 1 Pull CSB low 2 Send CLRCELL command 0x07 0x11 and its PEC 0xC9 0xC0 3 Pull CSB high Poll ADC Status Parallel configuration and ISOMD 0 This example uses an addressed LTC6804 2 with address A 3 0 0011 and ISOMD 0 1...

Page 56: ...e using STCOMM command a Pull CSB low b Send STCOMM command 0x07 0x23 and its PEC 0xB9 0xE4 c Send 72 clock cycles on SCK d Pull CSB high 3 Data transmitted to slave during the STCOMM com mandisstoredintheCOMMregister UsetheRDCOMM command to retrieve the data a Pull CSB low b Send RDCOMM command 0x07 0x22 and its PEC 0x32 0xD6 c Read COMM0 COMM5 and the PEC for the 6 bytes of data Assumingtheslave...

Page 57: ... bytes of data to SPI slave device using STCOMM command a Pull CSB low b Send STCOMM command 0x07 0x23 and its PEC 0xB9 0xE4 c Send 72 clock cycles on SCK d Pull CSB high 3 Data transmitted to slave during the STCOMM com mandisstoredintheCOMMregister UsetheRDCOMM command to retrieve the data a Pull CSB low b Send RDCOMM command 0x07 0x22 and its PEC 0x32 0xD6 c Read COMM0 COMM5 and the PEC for the...

Page 58: ...2V VREG 5V 40mA 1M 316k 1k 33µH BD FB GND OFF ON 680412 F29 1µF 0 1µF 100Ω 680412 F28 WDT DRIVE VREG SWTEN VREF1 VREF2 GPIO5 GPIO4 V V GPIO3 1µF 1µF LTC6804 NSV1C201MZ4 Improved Regulator Power Efficiency To minimize power consumption within the LTC6804 the current drawn on the V pin has been designed to be very small 500µA The voltage on the V pin must be at least as high as the top cell to provi...

Page 59: ... Source TEMPERATURE C 40 0 V TEMPx V REF2 100 80 60 40 20 90 70 50 30 10 0 20 20 60 40 80 680412 F31 10k NTC 10k AT 25 C V VREF2 VTEMP 680412 F30 DRIVE VREG V V LTC6804 100nF 100V CMHZ5265B 62V NSV1C201MZ4 CMHD459A PA0648NL CMMSH1 40 GND EN UVLO RFB LT8300 130k 100Ω SW VIN 1µF 10V 4 7µF 25V 7 2 8 1 5 4 1µF 100V 22 1k 100k 12V 52V 13V 12VRETURN 4 7µF 25V CONNECT TO TOP CELL current from conducting ...

Page 60: ...cuit showing the specific protection structures is shown in Figure 33 While pins 43 to 48 have different functionality for the 1 and 2 variants the protection structure is the same Zener likesuppressorsareshownwiththeirnominalclamp voltage otherdiodesexhibitstandardPNjunctionbehavior Figure 32 MUX Circuit Supports Sixteen Additional Analog Measurements Filtering of Cell and GPIO Inputs The LTC6804...

Page 61: ...s use a grounded capacitor configuration because the measurements are all with respect to V Figure 34 Input Filter Structure Configurations 680412 F33 LTC6804 10k 12V C12 S12 12V 10k 12V C11 S11 12V 10k 12V C10 S10 12V 10k 12V C9 S9 12V 10k 12V C8 S8 12V 10k 12V C7 S7 12V 10k 12V C6 S6 12V 10k 12V C5 S5 12V 10k 12V C4 S4 12V 10k 12V C3 S3 12V 10k 12V C2 S2 12V 10k 12V 25Ω C1 S1 12V C0 V V 30V 30V ...

Page 62: ...ws external MOSFET circuits that include RC filtering Figure 35 Internal Discharge Circuit Figure 36 External Discharge Circuit Table47 DischargeControlDuringanADCVCommandwithDCP 0 CELLMEASUREMENTPERIODS CELLCALIBRATIONPERIODS CELL1 7 CELL2 8 CELL3 9 CELL4 10 CELL5 11 CELL6 12 CELL1 7 CELL2 8 CELL3 9 CELL4 10 CELL5 11 CELL6 12 DISCHARGE PIN t0tot1M t1Mtot2M t2Mtot3M t3Mtot4M t4Mtot5M t5Mtot6M t6Mt...

Page 63: ... unacceptable levels Method to Verify Balancing Circuitry The functionality of the discharge circuitry is best verified by cell measurements Figure 37 shows an example using the LTC6804 battery monitor IC The resistor between the battery and the source of the discharge MOSFET causes cell voltage measurements to decrease The amount of measurement change depends on the resistor values and the MOSFET...

Page 64: ...TC6804 1 Applications Information Figure 37 Balancing Self Test Circuit 680412 F37 V C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 V C0 S1 LTC6804 RB1 RB1 RB2 RB1 RB2 RB1 RB2 RB1 RB2 RB1 RB2 RB1 RB2 RB1 RB2 RB1 RB2 RB1 RB2 RB1 RB2 RB1 RB2 RB2 ...

Page 65: ...ES WHATSOEVER RESULTING FROM ANY USE OF SAME INCLUDING ANY LOSS OF USE OR DATA OR PROFITS WHETHER IN AN ACTION OF CONTRACT NEGLIGENCE OR OTHER TORTUOUS ACTION ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE int16 pec15Table 256 int16 CRC15_POLY 0x4599 void init_PEC15_Table for int i 0 i 256 i remainder i 7 for int bit 8 bit 0 bit if remainder 0x4000 remainder remainder...

Page 66: ...izing cell voltage and cell current measurements Current Measurement with a Shunt Resistor ItispossibletomeasurethebatterycurrentontheLTC6804 GPIO pins with a high performance current sense ampli fier and a shunt Figure 39 shows 2 LTC6102s being used to measure the discharge and charge currents on a 12 cell battery stack To achieve a large dynamic range while maintaining a high level of accuracy t...

Page 67: ... a reading of 0V for those cells channels It is also acceptable to connect in the con ventional sequence with all unused cell inputs at the top isoSPI IBIAS and ICMP Setup The LTC6804 allows the isoSPI links of each application to be optimized for power consumption or for noise immunity The power and noise immunity of an isoSPI systemisdeterminedbytheprogrammedIBcurrent which controls the isoSPI s...

Page 68: ...loss in the cable and provides high noise immunity When using cables over 50m and a transformer with a 1 1 turns ratio andRM 100Ω RB1wouldbe1 5kandRB2wouldbe499Ω RM IPA ISOMD VREG IMA IBIAS ICMP 680412 F41 LTC6804 RM RB1 RB2 RB1 RB2 IPB ISOMD IMB IBIAS ICMP MOSI MISO SCK CS SDO SDI SCK CS LTC6804 TWISTED PAIR CABLE WITH CHARACTERISTIC IMPEDANCE RM ISOLATION BARRIER MAY USE ONE OR TWO TRANFORMERS M...

Page 69: ...se the addition of a split termination resistor and a bypass capacitor Figure 43a can enhance the isoSPI performance Large center tap capacitors greater than 10nF should be avoided as they may prevent the isoSPI common mode voltage from settling Common mode chokes similar to those used in Ethernet or CANbus applications are recommended Specific examples are provided in Table 49 isoSPI LINK XFMR is...

Page 70: ...1k GNDA GNDD GNDB GNDA 10nF GNDC 10nF 10nF 10nF 49 9Ω 49 9Ω IPA IBIAS ICMP LTC6804 1 IMA 49 9Ω 49 9Ω IPB IMB 49 9Ω 49 9Ω IPA IBIAS ICMP LTC6804 1 IMA 49 9Ω 49 9Ω IPB IMB 49 9Ω 49 9Ω IPA IBIAS ICMP IBIAS ICMP LTC6804 1 V V V IMA 49 9Ω 49 9Ω IP IM V 49 9Ω 49 9Ω IPB IMB IF TRANSFORMER BEING USED HAS A CENTER TAP IT SHOULD BE BYPASSED WITH A 10nF CAP 680412 F44 LTC6820 Figure 44 Daisy Chain Interface ...

Page 71: ...t is possible for a simplified capacitor isolated coupling as shown in Figure 45 to replace the transformer Dual Zener diodes are used at each IC to clamp the common mode voltage to stay within the receiver s input range The op tionalcommonmodechoke CMC providesnoiserejection withsymmetricallytappedtermination The590Ωresistor createsaresistordividerwiththeterminationresistorsand attenuatescommonmo...

Page 72: ...e transmission line will minimize reflections Connecting an MCU to an LTC6804 1 with an isoSPI Data Link The LTC6820 will convert standard 4 wire SPI into a 2 wire isoSPI link that can communicate directly with the LTC6804 An example is shown in Figure 46 The LTC6820 can be used in applications to provide isolation between the microcontroller and the stack of LTC6804s The LTC6820 also enables syst...

Page 73: ...ISOMD IMA V VREGC ICMP LTC6804 2 100Ω 1 21k 806Ω 5k 100nF IBIAS ICMP GND SLOW MSTR IP IM VDD VDDS EN MOSI MISO SCK CS POL PHA 5V 5V 5V 5V LTC6820 100nF µC SDO CS SDI SCK 100Ω Figure 47 Connecting the LTC6804 2 in a Multi Drop Configuration isoSPI BUS HV XFMR CT HV XFMR 22Ω 22Ω 22Ω 22Ω isoSPI BUS LTC6804 2 LTC6804 2 IPA IMA V 15pF 100µH CMC 10nF 100µH CMC 402Ω 15pF 402Ω a IPA IMA V 100µH CMC 10nF b...

Page 74: ... it is equally important to pick a part that has an adequate isolation rating for the application The working voltage rating of a transformer is a key spec when selecting a part for an application Table 48 Recommended Transformers MANUFACTURER PART NUMBER TEMPERATURE RANGE VWORKING VHIPOT 60s CT CMC H L W W LEADS PINS AEC Q200 Dual Transformers Pulse HX1188FNL 40 C to 85 C 60V est 1 5kVrms l l 6 0...

Page 75: ...iers Table48showsalistoftransformersthat have been evaluated in isoSPI links In most applications a common mode choke is also necessary for noise rejection Table 49 includes a list of suitable CMCs if the CMC is not already integrated into the transformer being used isoSPI Layout Guidelines Layout of the isoSPI signal lines also plays a significant role in maximizing the noise immunity of a data l...

Page 76: ...2 TYP MILLIMETERS INCHES DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE MOLD FLASH SHALL NOT EXCEED 15mm PER SIDE LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS DAMBAR PROTRUSIONS DO NOT EXCEED 0 13mm PER SIDE NOTE 1 DRAWING IS NOT A JEDEC OUTLINE 2 CONTROLLING DIMENSION M...

Page 77: ...PI master supports only SPI mode 3 Correction to data register Dn 3 0 changed to Dn 7 0 Discussion of Address Broadcast and Polling Commands edited for Clarity 4 5 20 22 27 27 51 28 30 51 30 31 32 43 46 C 10 16 Absolute maximum voltage between V to C12 Added Note added in table to define IB Explanation added for issuing ADSTAT command with CHST 100 Table 18 read codes for I2C master operation adde...

Page 78: ...Twisted Pair Companion to the LTC6804 LTC3300 High Efficiency Bidirectional Multicell Battery Balancer Bidirectional Synchronous Flyback Balancing of Up to 6 Li Ion or LiFeP04 Cells in Series Up to 10A Balancing Current Set by External Components Bidirectional Architecture Minimizes Balancing Time and Power Dissipation Up to 92 Charge Transfer Efficiency 48 Lead Exposed Pad QFN and LQFP Packages B...

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