Linear Technology LTC6804-1, Manual

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LTC6804-1/LTC6804-2
8
680412fc
For more information www.linear.com/LTC6804-1
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
LEAK(DIG)
Digital Input Current Pins CSB, SCK, SDI, ISOMD, SWTEN,
A0 to A3
l
±1 µA
V
OL(SDO)
Digital Output Low Pin SDO Sinking 1mA
l
0.3 V
isoSPI DC Specifications (See Figure 16)
V
BIAS
Voltage on IBIAS Pin READY/ACTIVE State
IDLE State
l
1.9 2.0
0
2.1 V
V
I
B
Isolated Interface Bias Current R
BIAS
= 2k to 20k
l
0.1 1.0 mA
A
IB
Isolated Interface Current Gain V
A
≤ 1.6V I
B
= 1mA
I
B
= 0.1mA
l
l
18
18
20
20
22
24.5
mA/mA
mA/mA
V
A
Transmitter Pulse Amplitude V
A
= |V
IP
– V
IM
|
l
1.6 V
V
ICMP
Threshold-Setting Voltage on ICMP
Pin
V
TCMP
= A
TCMP
• V
ICMP
l
0.2 1.5 V
I
LEAK(ICMP)
Input Leakage Current on ICMP Pin V
ICMP
= 0V to V
REG
l
±1 µA
I
LEAK(IP/IM)
Leakage Current on IP and IM Pins IDLE State, V
IP
or V
IM
= 0V to V
REG
l
±1 µA
A
TCMP
Receiver Comparator Threshold
Voltage Gain
V
CM
= V
REG
/2 to V
REG
– 0.2V, V
ICMP
= 0.2V to 1.5V
l
0.4 0.5 0.6 V/V
V
CM
Receiver Common Mode Bias IP/IM Not Driving (V
REG
– V
ICMP
/3 – 167mV) V
R
IN
Receiver Input Resistance Single-Ended to IPA, IMA, IPB, IMB
l
27 35 43 kΩ
isoSPI Idle/Wakeup Specifications (See Figure 21)
V
WAKE
Differential Wake-Up Voltage t
DWELL
= 240ns
l
200 mV
t
DWELL
Dwell Time at V
WAKE
Before Wake
Detection
V
WAKE
= 200mV
l
240 ns
t
READY
Startup Time After Wake Detection
l
10 µs
t
IDLE
Idle Timeout Duration
l
4.3 5.5 6.7 ms
isoSPI Pulse Timing Specifications (See Figure 19)
t
1/2PW(CS)
Chip-Select Half-Pulse Width
l
120 150 180 ns
t
INV(CS)
Chip-Select Pulse Inversion Delay
l
200 ns
t
1/2PW(D)
Data Half-Pulse Width
l
40 50 60 ns
t
INV(D)
Data Pulse Inversion Delay
l
70 ns
SPI Timing Requirements (See Figure 15 and Figure 20)
t
CLK
SCK Period (Note 4)
l
1 µs
t
1
SDI Setup Time before SCK Rising
Edge
l
25 ns
t
2
SDI Hold Time after SCK Rising
Edge
l
25 ns
t
3
SCK Low t
CLK
= t
3
+ t
4
≥ 1µs
l
200 ns
t
4
SCK High t
CLK
= t
3
+ t
4
≥ 1µs
l
200 ns
t
5
CSB Rising Edge to CSB Falling
Edge
l
0.65 µs
t
6
SCK Rising Edge to CSB Rising
Edge
(Note 4)
l
0.8 µs
t
7
CSB Falling Edge to SCK Rising
Edge
(Note 4)
l
1 µs
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. The test conditions are V
+
= 39.6V, V
REG
= 5.0V unless otherwise noted.