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Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
3. TECHNICAL BRIEF
The 5M Camera modules are connected to 34-pin main board and VGA Camera module
is connected to LCD FPCB with 20-pin Board to Board through 70 pin Board to Board
connector. VGA interface is dedicated camera interface port in DB3200, but 5 Mega
camera is connected to MMIC (Multi-media IC).
5 mega camera supply 24MHz master clock to camera module and receive 80MHz pixel
clock(30fps), vertical sync signal, horizontal sync signal, reset signal and 8bits YUV data
from camera module. The camera module is controlled by I2C port.
VGA camera port supply 24MHz master clock to camera module and receive 32.2MHz
pixel clock(15fps), vertical sync signal, horizontal sync signal, reset signal and 8bits YUV
data from camera module. The camera module is controlled by I2C port.
Table 3-2-2. Interface between VGA Camera Module
Table 3-2-1. Interface between Main board and 5M camera
Pin
Symbol
Symbol
Pin
1
M M P_CAM _M CLK
CAM _AVDD_2.8V
34
2
GND
GND
33
3
M M P_CAM _PCLK
CAM _VDD_1.8V
32
4
GND
CAM _VDD_1.8V
31
5
5M _CAM _DATA[0]
GND
30
6
5M _CAM _DATA[1]
M M P_CAM _RESET_N
29
7
5M _CAM _DATA[2]
GND
28
8
5M _CAM _DATA[3]
M M P_I2C_SDA
27
9
5M _CAM _DATA[4]
M M P_I2C_SCL
26
10 5M _CAM _DATA[5]
GND
25
11 5M _CAM _DATA[6]
M M P_CAM _VSYNC
24
12 5M _CAM _DATA[7]
M M P_CAM _HSYNC
23
13 5M _CAM _DATA[8]
GND
22
14 5M _CAM _DATA[9]
M M P_CAM _PWDN
21
15 5M _CAM _DATA[10]
GND
20
16 5M _CAM _DATA[11]
CAM _VDD_AF_2.8V
19
17 GND
GND
18
Pin
Symbol
Symbol
Pin
1
ACC_GP21_VC_IO_OFF
VGA_VDD_2.8V
20
2
SYSCLK0
VGA_VDD_1.8V
19
3
GND
CI_RES_n
18
4
CI_PCLK
APP_I2C_SCL
17
5
CI_D0
APP_I2C_SDA
16
6
CI_D1
VGA_VDD_1.8V
15
7
CI_D2
CI_HSYNC
14
8
CI_D3
CI_VSYNC
13
9
CI_D4
CI_D7
12
10 CI_D5
CI_D6
11
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