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LGE Internal Use Only
Copyright © 01 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
[ NAND Flash ]
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MULTIPLANE ARCHITECTURE
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SUPPLY VOLTAGE
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SUPPLY VOLTAGE
- Vcc = 1.7 - 1.95 V
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MEMORY CELL ARRAY
- (1K + 32) Words x 64 pages x 2048 blocks
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PAGE SIZE
- (1K+ 32 spare) Words
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BLOCK SIZE
- (64K + 2K spare) Words
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PAGE READ / PROGRAM
- Random access : 25us (max.)
- Sequential access : 45ns (min.)
- Page program time : 250us (typ.)
- Multi-page program time (2 pages): 250us (Typ.)
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BLOCK ERASE / MULTIPLE BLOCK ERASE
- Block erase time: 3.5 ms (Typ)
- Multi-block erase time (2 blocks): 3.5ms (Typ.)
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SEQURITY
- OTP area
- Sreial number (unique ID)
- Hardware program/erase disabled during
Hardware program/erase disabled during
- power transition
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ADDITIONAL FEATURE
- Multiplane Architecture:
Array is split into two independent planes.
Parallel operations on both planes are available, having program and erase time.
- Single and multiplane copy back program with auto matic EDC (error detection code)
- Single and multiplane page re-program
- Single and multiplane cache program
- Cache read
- Multiplane block erase
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RELIABILITY
- 100,000 Program / Erase cycles (with 1bit /528Byte ECC)
10 Year Data retention
ͽͶ͑ͺΟΥΖΣΟΒΝ͑ΆΤΖ͑ΟΝΪ
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- 10 Year Data retention
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ONFI 1.0 COMFLIANT COMMAND SET ELECTRICAL SIGNATURE
- Munufacture ID: ADh
- Device ID