45
RD15 /
DJ
17
I/O
RAM Data 15 / Drive Jumper:
RD15 is bit 15 of the RAM data bus. It is
also used as the DJ for the host interface.
RD14
18
I/O
RAM Data 14:
RD14 is bit 14 of the RAM data bus.
RD13 /
CPUTYPE
19
I/O
PU
RAM Data Bus 13/CPU Type:
RD13 is bit 13 of the RAM Data Bus. It is also
used as CPUTYPE for the system controller interface. (1 = Intel & 0 =
Motorola)
RD12 /
IFSEL
20
I/O
RAM Data Bus 12 / Interface Select:
RD12 is bit 12 of the RAM data bus
and also used as IFSEL for the host interface. (1
=
IDE
&
0
=
SCSI)
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
21
24
25
28
11
12
13
14
15
16
29
26
I/O
PU
RAM Data Bus
0:
RD
0 are bits 11–0 of the RAM data bus.
RRAS#
33
O
RAM Row Address Strobe:
In DRAM Mode, RRAS# indicates that RAD13 0
contains a row address. In SDRAM Mode, RRAS# is asserted to send the
row active command.
RWE# /
RWEL#
30
O
RAM Write Enable Low:
In dual-CAS# DRAM Mode, RWE# is indicates that
RD
0 is write data. For dual WE# DRAM mode, this signal enable writing
of the lower data byte (RD7
). In SDRAM mode, RWE# is asserted to
generate the write command.
ROE# /
LDQM
32
O
DRAM Output Enable:
In DRAM Mode, ROE# is asserted low to enable data
output.
SDRAM Data Mask Low:
In SDRAM Mode, LDQM is driven high to disable
RAM data output or block write data for RD7 0.
RCAS# /
RCASL#
31
O
RAM Column Address Strobe Low:
In DRAM Mode, RCAS# indicates that
RAD7
contains a column address. For dual-CAS# DRAM Mode, this
signal
is the column address strobe for the low data byte (R
In SDRAM Mode, RCAS# is asserted to generate the read/write command
and output the column address.
Pin Name
Pin #
Typ e
Description
