44
Pin Name
Pin #
Type
Description
RCLK
36
O
SDRAM System Clock:
RCLK clocks data and commands to/from the
SDRAM.
RCLKE
38
O
SDRAM Clock Enable:
RCLKE is asserted high to enable the SDRAM clock.
RCS#
37
O
SDRAM Chip Select:
RCS# is asserted low to select the SDRAM.
RAD13 /
RBA2
39
O
DRAM Row Address 13:
Row address 13 in EDO DRAM Mode
SDRAM Bank Address 2:
When RRCF (0CCh
selects 12 row address
signals, this signal is used as bank address bit 1
up to 4 banks
are
supported.
RAD12 /
RBA1
40
O
RAM Row/Column Address 12:
Row and column address 12
O
SDRAM Bank Address 1:
When RRCF (0CCh
selects 12 row address
signals, this signal is used as bank address bit 0
up to 4 banks
are
supported.
RAD11 /
RBA0
41
O
RAM Row/Column Address 11:
Row and column address 11
SDRAM Bank Address 0:
When RRCF (0CCh
selects 11 row address
signals, this signal is the only bank address signal
to 2 banks are
supported.
RAD10 /
RAP
42
O
RAM Row/Column Address 10:
This signal is row and column address 10.
O
SDRAM Auto-Precharge:
In SDRAM Mode during the read/write command,
this signal is used as auto-precharge and is asserted low to disable auto-
precharge.
RAD9
RAD8
RAD7
RAD6
RAD5
RAD4
RAD3
RAD2
RAD1
RAD0
43
44
45
48
49
50
51
52
53
54
O
RAM Row/Column Address
0:
These signals are row and column
address bits
0.
BUFFER MEMORY INTERFACE
