Pin No.
Pin Name
Type
Description
12~19
SA [15 :8]
IN
ADDRESS :
Use these pins when access through 64Kbyte buffer memory window.
ADDRESS :
20~27
SA [7 : 0]
IN
Use these pins in case of connection with a microprocessor which has separated
address and data bus.
29~32
SAD [7 : 0]
I/O (PU)
ADDRESS AND DATA : Address and data are multiplexed in a same pin.
34~37
In the case of input/output only data, fix SALE to GND.
These signals are Hi-Z when this LSI is reset.
ADDRESS LATCH ENABLE :
39
SALE
IN
Use this pin in case of connection with a microprocessor which has multiplexed
address and data bus.
READY : Data ready
40
SRDY
OUT
Selectable use/no use by setting internal registers.
(PU, TS)
In the case of access internal registers or buffer memory, this signal is asserted after
fixing driven data.
In case of no access, this pin is Hi-Z.
WRITE ENABLE/DATA READ WRITE STATUS : Write enable/data read write
status input for read.
41
SWEB/RWB
IN
In the case of CPUTYPE = Open (: 86 type), this pin is write enable.
In the case of CPUTYPE = GND (: 68 type), this pin is read/write status.
READ ENABLE/DATA STROBE : Read enable /data strobe input for read
42
SREB/DSB
IN
In the case of CPUTYPE = Open (: 86 type), this pin is read enable.
In the case of CPUTYPE = GND (: 68 type), this pin is data strobe.
43
CS1B
IN
CHIP SELECT 1 : Enable to access buffer memories.
44
CS0B
IN
CHIP SELECT 0 : Enable to access internal registers.
46
CPUTYPE
IN (PU)
CPU TYPE SELECT : Microprocessor type select
Open : 86 type
GND : 68 type
SYSTEM INTERRUPT REQUEST 0,1 :
47, 48
SINT1,
I/O (PU)
Possible output pin whether SINT1 or SINT0 by using internal registers at each
SINT0
interrupt groups (8bit unit)
SYSTEM RESET : Internal state machines are reset and all registers are set to default.
49
SRESB
IN (PU)
More than 1CLKIN active time is needed when assertion or negation of SRESB,
because it is through a de-glitch circuit.
System Controller Interface
44
