40
Notes :
•
The data at the 64-bit slot is output in 2's complements on an LSB-first basis.
The data at the 48-bit slot is output in 2's complements on an MSB-first basis.
•
GTOP monitors the state of Frame Sync protection. ("H" : Sync protection window released)
•
XUFG is a negative Frame Sync pulse obtained from the EFM signal before Frame Sync protection is
effected.
•
XPLCK is an inversion of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK
coincides with a change point of the EFM signal.
•
The GFS signal turns "H" upon coincidence between Frame Sync and the timing of interpolation protection.
•
RFCK is a signal generated at 136-
•Ï
s periods using a crystal oscillator.
•
C2PO is a signal to indicate data error.
•
XRAOF is a signal issued when a jitter margin of
°æ
28F is exceeded by the 32K RAM.
Pin No.
Symbol
I/O
Description
123
TES2
I
Test Pin. Normally "L"
124
TES3
I
Test Pin. Normally "L"
129
PWMI
I
External input of spindle motor
130
DV
DD
5
I
Digital power supply
131
VCOO
O
1, 0
Output of oscillation circuit analog EFM PLL
132
VCOI
I
Input to oscillation circuit for analog EFM PLL. f
LOCK
=8.6436MHz
133
TEST
I
Test Pin. Normally "L"
134
PDO
O
1, Z, 0
Output of charge pump for analog EFM PLL
135
VCKI
I
Clock input from external VCO for vari-pitch control. fc
center
=16.9344MHz
136
V16M
O
1, Z, 0
Output of VC02 oscillation for vari-pitch EFM PLL
137
AV
DD
2
Analog power supply
138
IGEN
I
Resistor connection pin of current source reference for OP Amp
139
AV
SS
2
Analog GND
140
ADIO
O
OP Amp output
141
RFDC
I
RF signal input
142
CE
I
Center servo analog input
143
TE
I
Tracking error signal input
