LeCroy LC564DL, Service Manual

Page: 31 / 210

Small Peripheral Interface
This 8-bit interface is intended to allow external expansion to the processor board.
A56 and A53 (74HCT541 tri-state buffers) buffer the address and control lines, and
A62 (74HCT245, bi-directional tri-state buffers) buffer the data lines.
The address decoding is done on each peripheral board. The acknowledge for
each access is also done by the peripheral device, so that there is no restriction on
wait-states. The bus clock runs at 16mhz, and a reset line reinitializes the boards at
the same time as the CPU.
Four interrupt lines are also included in this interface, so that interrupt-driven
boards can be used (a good example is the 9300-4 GPIB/RS232 board, which uses
interrupts 2 and 3).
Serial Interface for on-board Peripherals
Two GALs (SEVERE and SAVEUR) are used to access serial on-board devices,
like the real time clock, option GAL, front panel and some parts of the acquisition
board. The principle of such a serial access is the following:
every write or read to the serial interface allows to write or read one bit (the MSB of
the byte). To write a byte to a serial device, you need eight accesses to the serial
interface.
Many serial devices need the same protocol: you first send a command byte (read,
write, clear, etc.), and then read or write one or several data (if required).
Depending on the address the serial interface is been accessed, the corresponding
device gets selected (_SSER, _SFPR, _SLED or SRTC lines). A clock (_SCKA), a
read data (SDRA or SDRD) and a write data (SDWA or SDWD) constitute the serial
interface itself (the D suffix on read and write data lines means Digital, i.e. devices
on the CPU board; an A suffix means devices on the Acquisition board).
RTC
The 68HC68T1 real time clock has several functions:
•
keep a time-of-the-day and current-date information while the DSO is not
powered on.
•
generate a 32kHz clock for DRAM refreshment.
•
generate a 128Hz periodic interrupt to force bus accesses from the processor
(otherwise the watchdog timer would time out and reset the board) and allow
periodic update of the time display (“scope alive”).
The chip uses it’s own 32.768kHz crystal to keep the time and derive all timings. A
few discrete components around it leave the chip powered by the backup lithium
battery while the rest of the board is not powered, and charge the battery when the
power is on again.
Front Panel
The front panel LED can be controlled by a serial write access. The LED (write
only) shares the same address as the option GAL (read only).
The LED is driven by the less significant bit (LSB) of the control register.
Watchdog and Reset Generation
Theory of Operation 4-7