LeCroy LC564DL, Service Manual

Page: 4 / 210

ii Table of Contents
Theory of Operation
Memory
Mapping 4-4
VGA 4-4
9601-2 Board: VGA proper termination 4-4
Bus Sizer 4-5
16 and 8-bit peripherals 4-5
PCMCIA Interface 4-5
Flash Prom 4-6
NVRAM 4-6
Interrupt Controller 4-6
Floppy Controller 4-6
Centronics 4-6
Small Peripheral Interface 4-7
Serial Interface For On Board Peripherals 4-7
RTC 4-7
Front Panel 4-7
Watchdog and Reset Generation 4-8
Bus Error Generation 4-8
I/O Structure & GAL's Installed 4-8
Figure 4-2: Peripheral Decoding and Data Bus Size 4-9
4.2 900079 Main Acquisition Board 4-10
4.2.1 Introduction 4-10
4.2.2 Front End 4-10
Front End Power off State 4-11
Figure 4-3: Front End Power off State 4-11
50Ohm Input Direct Path 4-12
Figure 4-4: 50Ohm Input Direct Path 4-12
50Ohm Input Divide by 10 Path 4-12
Figure 4-5: 50Ohm Input Divide by 10 Path 4-12
1 MOhm Direct Path 4-13
Figure 4-6: 1 MOhm Direct Path 4-13
I Mohm Input Divide by 10 AC Coupled Path 4-13
Figure 4-7: 1 Mohm Divide by 10 AC Coupled 4-13
Front end analog controls 4-13
4.2.3 Main Acquisition Board Block Diagram 4-14
Figure 4-8: Front End, Trigger, Sample & Hold, ADC 4-14
4.2.4 One, Two and Four Channel Mode 4-15
Four Channel Mode 4-15
Figure 4-9 Four Channel Mode Signal Routing 4-15
Two Channel Mode 4-15
Figure 4-10 Two Channel Mode Signal Routing 4-15
4.2.4 Control & Transfer Block Diagram 4-16
Figure 4-11: Processor Control, Min/Max, Buffer Memory 4-16
4.2.5 Trigger 4-17
Analog Controls 4-17
TV Trigger 4-17
4.2.6 Analog to Digital Converter 4-17
Introduction 4-17