LeCroy LC564DL, Service Manual

Page: 32 / 210

4-8 Theory of Operation
The power supply is monitored by a TL7770-5 chip. Whenever the Vcc voltage
goes below 4.8V (even for a short time !), a reset pulse is generated, whose width
is determined by an RC time constant (33uF and internal resistor).
The second half of this chip serves as watchdog circuit. The processor needs to
poll a sense line on that chip from time to time (typically a few ms). By doing this, a
capacitor (33uF) is discharged. When not polled, it gets charged by a constant
current, and when a given threshold is exceeded, a reset pulse is generated.
The LED connected goes off whenever the _RESET line is low, so a blinking LED
indicates either no bus access for longer than a few hundreds of ms, or a problem
(glitch) on the Vcc power supply.
Bus Error Generation
A bus error exception is generated when the _TEA pin is pulled low on the
processor. The 603e expects a _TA signal as an acknowledge to the current data
transaction, and inserts wait states as long as _TA has not been pulled low at the
correct timing (refer to the MPC603e documentation for exact timing information’s).
An external circuit is required to break the pending cycle if no device responds after
a given time-out.
This is the job of the GAL RETINE (A36), which counts the number of wait states
already passed (4 bit Gray counter). An external 4-bit counter (A59) extends the
count to 160 (tbd) wait cycles before triggering a bus error.
An acknowledge (_DSACK1..0 lines) aborts the time-out count and finishes
successfully the current cycle.
I/O Structure and GALs Involved
The following bloc diagram describes the peripheral decoding flow, and what GAL
is involved in the decoding. The three frames group the peripherals into 8, 16 or 32-
bit devices. The simple 3D-blocs represent an on-board device. The 3D-blocks with
an arrow represent external devices (more generally: accessed through a
connector).
GRANDS does the main decoding of peripherals and the 93xx-3 acquisition board.
PETITS does the sub-decoding for all 8-bit peripherals.
VIADUC handles the Motorola to Intel format decoding for the VGA controller.
CARDAN takes care of the PCMCIA interface timings.
PROFIL dispatches 8-bit data to the Centronics or the Floppy controller.
SAVEUR and SEVERE generate the serial clock and routes the data to the right
serial device, including CLExxx, which is the option PAL.