C5000 Debugger | 23
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<parameters> describing the “JTAG” scan chain and signal behavior
With the JTAG interface you can access a Test Access Port controller (TAP) which has implemented a state
machine to provide a mechanism to read and write data to an Instruction Register (IR) and a Data Register
(DR) in the TAP. The JTAG interface will be controlled by 5 signals:
•
nTRST (reset)
•
TCK (clock)
•
TMS (state machine control)
•
TDI (data input)
•
TDO (data output)
Multiple TAPs can be controlled by one JTAG interface by daisy-chaining the TAPs (serial connection). If you
want to talk to one TAP in the chain, you need to send a BYPASS pattern (all ones) to all other TAPs. For this
case the debugger needs to know the position of the TAP it wants to talk to. The TAP position can be defined
with the first four commands in the table below.
…
DRPOST
<bits>
Defines the TAP position in a JTAG scan chain. Number of TAPs in the
JTAG chain between the TDI signal and the TAP you are describing. In
BYPASS mode, each TAP contributes one data register bit. See possible
TAP types and example below.
Default: 0.
…
DRPRE
<bits>
Defines the TAP position in a JTAG scan chain. Number of TAPs in the
JTAG chain between the TAP you are describing and the TDO signal. In
BYPASS mode, each TAP contributes one data register bit. See possible
TAP types and example below.
Default: 0.
…
IRPOST
<bits>
Defines the TAP position in a JTAG scan chain. Number of Instruction
Register (IR) bits of all TAPs in the JTAG chain between TDI signal and
the TAP you are describing. See possible TAP types and example below.
Default: 0.
…
IRPRE
<bits>
Defines the TAP position in a JTAG scan chain. Number of Instruction
Register (IR) bits of all TAPs in the JTAG chain between the TAP you are
describing and the TDO signal. See possible TAP types and example
below.
Default: 0.
NOTE:
If you are not sure about your settings concerning
,
and
, you can try to detect the settings automatically with the
command.