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C5000 Debugger | 45

©

1989-2022

Lauterbach

…

PORT

<port>

Informs the debugger about which trace source is connected to
which input port of which funnel. A CoreSight trace funnel
provides 8 input ports (port 0-7) to combine the data of various
trace sources to a common trace stream.

Example

: SYStem.CONFIG STMFUNNEL2PORT 3

Meaning: The System Trace Module (STM) is connected to input
port #3 on FUNNEL2.

On an SMP debug session some of these commands can have a
list of

<port>

parameter.

In case there are dedicated funnels for the ETB and the TPIU
their base addresses are specified by ETBFUNNELBASE,
TPIUFUNNELBASE respectively. And the funnel port number for
the ETM are declared by ETMETBFUNNELPORT,
ETMTPIUFUNNELPORT respectively.

TRACE... stands for the ADTF trace source module.

For a list of possible components including a short description
see

Components and Available Commands

CTICONFIG

<type>

Informs about the interconnection of the core Cross Trigger
Interfaces (CTI). Certain ways of interconnection are common
and these are supported by the debugger e.g. to cause a
synchronous halt of multiple cores.

NONE: The CTI is not used by the debugger.
ARMV1: This mode is used for ARM7/9/11 cores which support
synchronous halt, only.
ARMPostInit: Like ARMV1 but the CTI connection differs from the
ARM recommendation.
OMAP3: This mode is not yet used.
TMS570: Used for a certain CTI connection used on a TMS570
derivative.
CortexV1: The CTI will be configured for synchronous start and
stop via CTI. It assumes the connection of DBGRQ, DBGACK,
DBGRESTART signals to CTI are done as recommended by
ARM. The CTIBASE must be notified. “CortexV1” is the default
value if a Cortex-A/R core is selected and the CTIBASE is
notified.
QV1: This mode is not yet used.

TIOCPTYPE

<type>

Specifies the type of the OCP module from Texas Instruments
(TI).

view

Opens a window showing most of the SYStem.CONFIG settings
and allows to modify them.

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Summary of Contents for C5000 Debugger

Page 1: ...MANUAL Release 02 2022 C5000 Debugger ...

Page 2: ... while HLL single stepping 9 SYStem CPU Select the used CPU 9 SYStem JtagClock Define JTAG frequency 10 SYStem MemAccess Run time memory access 11 SYStem Mode Establish the communication with the target 12 SYStem CONFIG state Display target configuration 13 SYStem CONFIG Configure debugger according to target topology 15 parameters describing the DebugPort 20 parameters describing the JTAG scan ch...

Page 3: ...cesses 56 SYStem RESetOut Reset the DSP 56 SYStem Option CToolsDecoder Use TI s trace decoder software 57 SYStem Option CtoolsNoSync CToolsNoSync 57 CPU specific BenchMarkCounter Commands 58 BMC counter ATOB Advise counter to count within AB range 58 BMC counter EVENT Assign event to counter 59 TrOnchip Commands 60 TrOnchip state Display on chip trigger window 60 TrOnchip CONVert Adjust range brea...

Page 4: ...C5000 Debugger 4 1989 2022 Lauterbach Mechanical Description of the TI Connector 71 FAQ 71 Operation Voltage 72 ...

Page 5: ... that are specific for the processor architecture supported by your debug cable To access the manual for your processor architecture proceed as follows Choose Help menu Processor Architecture Manual OS Awareness Manuals rtos_ os pdf TRACE32 PowerView can be extended for operating system aware debugging The appropriate OS Awareness manual informs you how to enable the OS aware debugging Converter f...

Page 6: ...he target while the target power is off 2 Connect the host system the TRACE32 hardware and the Debug Cable 3 Power ON the TRACE32 hardware 4 Start the TRACE32 software to load the debugger firmware 5 Connect the Debug Cable to the target 6 Switch the target power ON 7 Configure your debugger e g via a start up script Power down 1 Switch off the target power 2 Disconnect the Debug Cable from the ta...

Page 7: ... resources to set the breakpoints are provided by the CPU Those CPU resources only allow to set single address instruction breakpoints On chip Breakpoints for Data To stop the CPU after a read or write access to a memory location on chip breakpoints are required In the DSP notation these breakpoints are called watch points WP Overview On chip breakpoints Total amount of available on chip breakpoin...

Page 8: ...akpoints Instruction breakpoints Read Write breakpoint Data Value breakpoints C54x 2 2 single address C55x 4 up to 4 single address up to 3 data 1 breakpoint range and 2 bit masks up to 3 Memory Class Description P Program Memory D Data Memory IO Input Output Area VM Virtual Memory memory on the debug system E Emulation Memory Pseudo Dualport Access to Memory see SYStem CpuAccess Data dump IO 0 3 ...

Page 9: ... IMASKHLL Disable interrupts while HLL single stepping Default OFF Interrupts are disabled during HLL single step operations if this option is ON SYStem CPU Select the used CPU Default selection C55XX Selects the processor type If your ASIC is not listed select the type of the integrated DSP core Format SYStem Option IMASKASM ON OFF Format SYStem Option IMASKHLL ON OFF Format SYStem CPU cpu cpu C5...

Page 10: ...TCK signal Returned TCK On some processor derivatives including an ARM core e g OMAP there is the need to synchronize the processor clock and the JTAG clock In this case RTCK shall be selected Synchronization is maintained because the debugger does not progress to the next TCK edge until after an RTCK edge is received When RTCK is selected the maximum reachable frequency is limited to 10 MHz This ...

Page 11: ...TDO SWDIO signal will be sampled by the RTCK signal This compensates the debugger internal driver propagation delays the delays on the cable and on the target Compensation by RTCK This feature requires that the target provides an RTCK signal In contrast to the RTCK option the TCK SWCLK is always output with the selected fixed frequency Format SYStem MemAccess mode mode Enable Denied StopAndGo Enab...

Page 12: ... shall not be debugged or bypassed i e the debugger can access the memory busses such as AXI AHB and APB directly through the memory access ports of the CoreSight DAP Typical use cases The debugger accesses physical memory and bypasses the CPU if a mapping exists Memory might require initialization before it can be accessed The debugger accesses peripherals e g for configuring registers prior to s...

Page 13: ...be stopped with the Break command StandBy Keeps the target in reset via the reset line and waits until power is detected For a reset the reset line has to be connected to the debug connector Once power has been detected the debugger restores as many debug registers as possible e g on chip breakpoints vector catch events trace control and releases the CPU from reset to start the program execution W...

Page 14: ...e of a System Chip Level Test Access Port The debugger might need to control it in order to reconfigure the JTAG chain or to control power clock reset and security of different chip components For descriptions of the commands on the MultiTap tab see MultiTap AccessPorts This tab informs the debugger about an Arm CoreSight Access Port AP and about how to control the AP to access chip internal memor...

Page 15: ...F SWDP ON OFF C7000 only SWDPIdleHigh ON OFF SWDPTargetSel value TriState ON OFF parameter JTAG cont DAPDRPOST bits DAPDRPRE bits DAPIRPOST bits DAPIRPRE bits DRPOST bits DRPRE bits ETBDRPOST bits C5000 only ETBDRPRE bits C5000 only ETBIRPOST bits C5000 only ETBIRPRE bits C5000 only parameter JTAG cont IRPOST bits IRPRE bits Slave ON OFF TAPState state TCKLevel level TriState ON OFF parameter Mult...

Page 16: ... port AXIAPn RESet AXIAPn view AXIAPn XtorName name DEBUGAPn Port port DEBUGAPn RESet DEBUGAPn view DEBUGAPn XtorName name JTAGAPn Base address JTAGAPn Port port JTAGAPn CorePort port JTAGAPn RESet JTAGAPn view JTAGAPn XtorName name parameter AccessPorts cont MEMORYAPn HPROT value name MEMORYAPn Port port MEMORYAPn RESet MEMORYAPn view MEMORYAPn XtorName name parameter COmponents ADTF Base address...

Page 17: ...iew DRM Base address DRM RESet DRM view EPM Base address EPM RESet EPM view ETB ATBSource source ETB Base address ETB Name string ETB NoFlush ON OFF ETB RESet ETB Size size ETB STackMode NotAvailbale TRGETM FULLTIDRM NOTSET FULL STOP FULLCTI ETB view parameter COmponents cont FUNNEL ATBSource sourcelist FUNNEL Base address FUNNEL Name string FUNNEL PROGrammable ON OFF FUNNEL RESet FUNNEL view OCP ...

Page 18: ...s TBR Name string TBR NoFlush ON OFF TBR RESet TBR STackMode NotAvailbale TRGETM FULLTIDRM NOTSET FULL STOP FULLCTI TBR view TPIU ATBSource source TPIU Base address TPIU Name string TPIU RESet TPIU Type CoreSight Generic TPIU view parameter Components cont TRACEPORT Name TRACEPORT RESet TRACEPORT TraceSource TRACEPORT Type TRACEPORT view TRC Base address C7000 only TRC RESet C7000 only TRC view C7...

Page 19: ... further SYStem CONFIG command The SYStem CONFIG command information shall be provided after the SYStem CPU command which might be a precondition to enter certain SYStem CONFIG commands and before you start up the debug session e g by SYStem Up parameter Deprecated cont FUNNEL2BASE address FUNNELBASE address HTMBASE address ITMBASE address RTPBASE address SDTIBASE address STMBASE address TIADTFBAS...

Page 20: ...nd might be required in a multicore environment if you use multiple debugger instances multiple TRACE32 PowerView GUIs to simultaneously debug different cores on the same target system Because of the default setting of this command debugger 1 core 1 chip 1 debugger 2 core 1 chip 2 each debugger instance assumes that all notified debug and trace resources can exclusively be used But some target sys...

Page 21: ...bleA DebugCableB It specifies which probe cable shall be used e g DebugCableA or DebugCableB At the moment only the CombiProbe allows to connect more than one probe cable Default depends on detection DEBUGPORTTYPE JTAG SWD CJTAG CJTAGSWD It specifies the used debug port type JTAG SWD CJTAG CJTAG SWD It assumes the selected type is supported by the target Default JTAG What is NIDnT NIDnT is an acro...

Page 22: ...ock on the SWCLK line is stopped kept low You can configure the debugger to pull the SWDIO data line high when no operation is in progress by using SYStem CONFIG SWDPIdleHigh ON Default OFF SWDPTargetSel value Device address in case of a multidrop serial wire debug port Default none set any address accepted TriState ON OFF TriState has to be used if several debug cables are connected to a common J...

Page 23: ...mber of TAPs in the JTAG chain between the TDI signal and the TAP you are describing In BYPASS mode each TAP contributes one data register bit See possible TAP types and example below Default 0 DRPRE bits Defines the TAP position in a JTAG scan chain Number of TAPs in the JTAG chain between the TAP you are describing and the TDO signal In BYPASS mode each TAP contributes one data register bit See ...

Page 24: ...able 0 Exit2 DR 1 Exit1 DR 2 Shift DR 3 Pause DR 4 Select IR Scan 5 Update DR 6 Capture DR 7 Select DR Scan 8 Exit2 IR 9 Exit1 IR 10 Shift IR 11 Pause IR 12 Run Test Idle 13 Update IR 14 Capture IR 15 Test Logic Reset Default 7 Select DR Scan TCKLevel level Level of TCK signal when all debuggers are tristated Normally defined by a pull up or pull down resistor on the target Default 0 TriState ON O...

Page 25: ...emory access changes the JTAG chain and the core TAP position then you can specify the new values with the NEXT parameter After the access for example the parameter NEXTIRPRE will replace the IRPRE value and NEXTIRPRE becomes 0 Available only on ARM11 debugger NEXTDRPOST NEXTDRPRE NEXTIRPOST NEXTIRPRE RTP RAM Trace Port TAP if the RTP has its own TAP to access its control register RTPDRPOST RTPDRP...

Page 26: ...C5000 Debugger 26 1989 2022 Lauterbach ...

Page 27: ...ts different versions Icepickx STCLTAPx MSMTAP Example DAPTAP tap Specifies the TAP number which needs to be activated to get the DAP TAP in the JTAG chain Used if MULTITAP Icepickx DEBUGTAP tap Specifies the TAP number which needs to be activated to get the core TAP in the JTAG chain E g ARM11 TAP if you intend to debug an ARM11 Used if MULTITAP Icepickx ETBTAP tap Specifies the TAP number which ...

Page 28: ...tialize the MSMTAP Please note some of these parameters need a decimal input dot at the end IcepickXY means that there is an Icepick version X which includes a subsystem with an Icepick of version Y For a description of the JtagSEQuence subcommands see SYStem CONFIG MULTITAP JtagSEQuence NJCR tap Number of a Non JTAG Control Register NJCR which shall be used by the debugger Used if MULTITAP Icepic...

Page 29: ...especially important if the core you intend to debug is connected to such an internal JTAG interface The module controlling these JTAG interfaces is called JTAG Access Port JTAG AP Each JTAG AP can control up to 8 internal JTAG interfaces A port number between 0 and 7 denotes the JTAG interfaces to be addressed 3 A transactor name for virtual connections to AMBA bus level transactors can be config...

Page 30: ...used for the HPROT bits in the Control Status Word CSW of a CoreSight AXI Access Port when using the AXI memory class MEMORYAPn HPROT value name Default 0 This option selects the value used for the HPROT bits in the Control Status Word CSW of a CoreSight Memory Access Port when using the E memory class SoC 600 Debug link s Memory System 3 ROM table ROM table CoreSight Component CoreSight Component...

Page 31: ...0x3 Cache 0x0 This option configures the value used for the Cache and Domain bits in the Control Status Word CSW 27 24 Cache CSW 14 13 Domain of an Access Port when using the AXI memory class name Description DeviceSYStem 0x30 Domain 0x3 Cache 0x0 NonCacheableSYStem 0x32 Domain 0x3 Cache 0x2 ReadAllocateNonShareable 0x06 Domain 0x0 Cache 0x6 ReadAllocateInnerShareable 0x16 Domain 0x1 Cache 0x6 Rea...

Page 32: ... XtorName name APB bus transactor name identifying the bus where the debug register can be found Used for DAP access class MEMORYAPn XtorName name AHB bus transactor name identifying the bus where system memory can be accessed even during runtime Used for E access class while running assuming SYStem MemAccess DAP RESet Undo the configuration for this access port This does not cause a physical rese...

Page 33: ...ass Default port not available DEBUGAPn Port port DEBUGACCESSPORT port deprecated AP access port number 0 255 of a SoC 400 system where the debug register can be found typically on APB Used for DAP access class Default port 1 JTAGAPn CorePort port COREJTAGPORT port deprecated JTAG AP port number 0 7 connected to the core which shall be debugged JTAGAPn Port port JTAGACCESSPORT port deprecated Acce...

Page 34: ...NFIG APBAP1 Base DP 0x80003000 Meaning The control register block of the APB access ports starts at address 0x80003000 AXIAPn Base address This command informs the debugger about the start address of the register block of the AXIAPn access port And this way it notifies the existence of the access port An access port typically provides a control register block which needs to be accessed by the debu...

Page 35: ...trace components your chip includes and which you intend to use with the debugger s help Each configuration can be done by a command in a script file as well Then you do not need to enter everything again on the next debug session If you press the button with the three dots you get the corresponding command in the command line where you can view and maybe copy it into a script file ...

Page 36: ...in most cases Example SYStem CONFIG COREDEBUG Base 0x80010000 0x80012000 SYStem CONFIG BMC Base 0x80011000 0x80013000 SYStem CONFIG ETM Base 0x8001c000 0x8001d000 SYStem CONFIG STM1 Base EAHB 0x20008000 SYStem CONFIG STM1 Type ARM SYStem CONFIG STM1 Mode STPv2 SYStem CONFIG FUNNEL1 Base 0x80004000 SYStem CONFIG FUNNEL2 Base 0x80005000 SYStem CONFIG TPIU Base 0x80003000 SYStem CONFIG FUNNEL1 ATBSou...

Page 37: ...be the interconnection by ATBSource source A CoreSight trace FUNNEL has eight input ports port 0 7 to combine the data of various trace sources to a common trace stream Therefore you can enter instead of a single source a list of sources and input port numbers Example SYStem CONFIG FUNNEL ATBSource ETM 0 HTM 1 STM 7 Meaning The funnel gets trace data from ETM on port 0 from HTM on port 1 and from ...

Page 38: ... exists only for FUNNELs For a list of possible components including a short description see Components and Available Commands BASE address This command informs the debugger about the start address of the register block of the component And this way it notifies the existence of the component An on chip debug and trace component typically provides a control register block which needs to be accessed...

Page 39: ...EL RESet Undo the configuration for this component This does not cause a physical reset for the component on the chip For a list of possible components including a short description see Components and Available Commands view Opens a window showing the current configuration of the component For a list of possible components including a short description see Components and Available Commands TraceID...

Page 40: ...rt stop events from and to the CTIs ARMv8 only ARMV8V3 Channel 0 1 and 2 of the CTM are used to distribute start stop events Implemented on request ARMv8 only ETB NoFlush ON OFF Deactivates an ETB flush request at the end of the trace recording This is a workaround for a bug on a certain chip You will loose trace data at the end of the recording Don t use it if not needed Default OFF ETB Size size...

Page 41: ... OCP module The type is just a number which you need to figure out in the chip documentation RTP PerBase address PERBASE specifies the base address of the core peripheral registers which accesses shall be traced PERBASE is needed for the RAM Trace Port RTP which is available on some derivatives from Texas Instruments The trace packages include only relative addresses to PERBASE and RAMBASE RTP Ram...

Page 42: ...ulation Pin Manager EPM Texas Instruments It will be used to prepare chip pins for trace output ETB ATBSource source ETB Base address ETB RESet ETB Size size Embedded Trace Buffer ETB ARM CoreSight module Enables trace to be stored in a dedicated SRAM The trace data will be read out through the debug port after the capturing has finished FUNNEL ATBSource sourcelist FUNNEL Base address FUNNEL Name ...

Page 43: ...Base address SC RESet SC TraceID id Statistic Collector SC Texas Instruments Trace source delivering statistic data about bus traffic to a system trace module STM Base address STM Mode NONE XTIv2 SDTI STP STP64 STPv2 STM RESet STM Type None Generic ARM SDTI TI System Trace Macrocell STM MIPI ARM CoreSight others Trace source delivering system trace information e g sent by software in printf style ...

Page 44: ...essible via APB bus In an SMP Symmetric MultiProcessing debug session you can enter for the components BMC CORE CTI ETB ETF ETM ETR a list of base addresses to specify one component per core Example assuming four cores SYStem CONFIG COREBASE 0x80001000 0x80003000 0x80005000 0x80007000 COREBASE old syntax DEBUGBASE Some cores e g Cortex A or Cortex R do not have a fix location for their debug regis...

Page 45: ...nd Available Commands CTICONFIG type Informs about the interconnection of the core Cross Trigger Interfaces CTI Certain ways of interconnection are common and these are supported by the debugger e g to cause a synchronous halt of multiple cores NONE The CTI is not used by the debugger ARMV1 This mode is used for ARM7 9 11 cores which support synchronous halt only ARMPostInit Like ARMV1 but the CTI...

Page 46: ...NNEL2PORT port FUNNEL2 ATBSource DTM port 1 DTMFUNNELPORT port FUNNEL1 ATBSource DTM port 1 DTMTPIUFUNNELPORT port FUNNEL3 ATBSource DTM port 1 DWTBASE address DWT Base address ETB2AXIBASE address ETB2AXI Base address ETBBASE address ETB1 Base address ETBFUNNELBASE address FUNNEL4 Base address ETFBASE address ETF1 Base address ETMBASE address ETM Base address ETMETBFUNNELPORT port FUNNEL4 ATBSourc...

Page 47: ...ress SDTIBASE address STM1 Base address STM1 Mode SDTI STM1 Type SDTI STMBASE address STM1 Base address STM1 Mode STPV2 STM1 Type ARM STMETBFUNNELPORT port FUNNEL4 ATBSource STM1 port 1 STMFUNNEL2PORT port FUNNEL2 ATBSource STM1 port 1 STMFUNNELPORT port FUNNEL1 ATBSource STM1 port 1 STMTPIUFUNNELPORT port FUNNEL3 ATBSource STM1 port 1 TIADTFBASE address ADTF Base address TIDRMBASE address DRM Bas...

Page 48: ...he DAP AXI AP including barriers This does only work if the debug logic of the target CPU implements coherent AXI accesses Otherwise this option will be without effect SYStem Option AXICACHEFLAGS Configure AXI AP cache bits Default DeviceSYStem 0x30 Domain 0x3 Cache 0x0 TRACEFUNNELPORT port FUNNEL1 ATBSource ADTF port 1 TRACETPIUFUNNELPORT port FUNNEL3 ATBSource ADTF port 1 view state Format SYSte...

Page 49: ...ht AXI Access Port when using the AXI memory class SYStem Option ByteMode Define byte mode Default AUTO Defines byte mode SYStem Option DAPDBGPWRUPREQ Force debug power in DAP Default ON Format SYStem Option AXIHPROT value deprecated Use SYStem CONFIG AXIAPn HPROT instead Format SYStem Option ByteMode AUTO ACCESS WORD BYTE AUTO Byte mode is automatically detected by TRACE32 ACCESS The selected byt...

Page 50: ... because they cannot access the debug interface anymore To keep the debug interface active it is recommended that SYStem Option DAPDBGPWRUPREQ is set to AlwaysON SYStem Option DAPSYSPWRUPREQ Force system power in DAP Default ON ON Debug power is requested by the debugger on a debug session start and the control bit is set to 1 The debug power is released at the end of the debug session and the con...

Page 51: ... requested by the debugger on a debug session start and the control bit is set to 1 The system power is not released at the end of the debug session and the control bit remains at 1 ON System power is requested by the debugger on a debug session start and the control bit is set to 1 The system power is released at the end of the debug session and the control bit is set to 0 OFF System power is not...

Page 52: ...improper switching sequences Therefore this succeeds in most cases None There is no switching sequence required The SW DP is ready after power up The debug port of this device can only be used as SW DP JtagToSwd Switching procedure as it is required on SWJ DP without a dormant state The device is in JTAG mode after power up LuminaryJtagToSwd Switching procedure as it is required on devices from Lu...

Page 53: ...hat nRESET nSRST becomes active at the start of a debug session SYStem Up but there may be other logic on the target which requires a reset SYStem LOCK Tristate the JTAG port Default OFF If the system is locked no access to the JTAG port will be performed by the debugger While locked the JTAG connector of the debugger is tristated The intention of the SYStem LOCK command is for example to give JTA...

Page 54: ...the TMS method is used The reason for introducing this command was that in some target systems several chips were connected to the TRST line which must not be reset together with the debug TAP SYStem Option INTDIS Disable all interrupts Default OFF If this option is ON all interrupts on the core are disabled SYStem Option MUHP High priority memory access Default OFF Format SYStem Option EnTRST ON ...

Page 55: ...This enables the debugger to handle overlaid program memory OFF Disables support for code overlays WithOVS Like option ON but also enables support for software breakpoints This means that TRACE32 writes software breakpoint opcodes to both the execution area for active overlays and the storage area This way it is possible to set breakpoints into inactive overlays Upon activation of the overlay the ...

Page 56: ... SYStem Option TURBO Use DMA for write accesses Default OFF If TURBO is enabled the debugger uses a DMA channel of the DSP to write data to the DSP memory area This option doubles the download rate In case the user application uses the same DMA resource the transfer will not work Therefore we recommend to use that option for downloading data after reset at the beginning of a debug session only SYS...

Page 57: ... LAUTERBACH trace decoder software is optimized for TRACE32 software architecture However TI CToolsDecoder might be helpful for error diagnostics SYStem Option CtoolsNoSync CToolsNoSync Default OFF Some first generation chips with C55x cTools trace functionality do not generate synchronization sequences In that very untypical case this option has to be set to ON Normally this option is not require...

Page 58: ...count within AB range Advise the counter to count the specified event only in AB range Alpha and Beta markers are used to specify the AB range Example to measure the time used by the function sieve Format BMC counter ATOB ON OFF BMC counter ClockCylces counter counts clock cycles BMC CLOCK 450 Mhz core is running at 450 MHz Break Set sieve Alpha set a marker Alpha to the entry of the function siev...

Page 59: ...to total instruction access INST Instructions PINST Parallel instructions INT Interrupts PNULL Pipe protection NULL FNULL Instruction fetch NULL DNULL Data fetch NULL DCMISS Data cache misses Counts data cache misses in relation to total data access DCACOLL Data cache arbitration collisions IDLE Idle clock cycles D Delta breakpoints E Echo breakpoints CLOCKCYCLES Clock cycles TIME TIME is measured...

Page 60: ...e converted into a single address breakpoint when this option is active This is the default Otherwise an error message is generated Format TrOnchip state Format TrOnchip CONVert ON OFF deprecated Use Break CONFIG InexactAddress instead TrOnchip CONVert ON Break Set 0x1000 0x17ff Write Break Set 0x1001 0x17ff Write TrOnchip CONVert OFF Break Set 0x1000 0x17ff Write Break Set 0x1001 0x17ff Write set...

Page 61: ...ha and Beta only TrOnchip BMCTR Configure the benchmark counter Benchmark Counter short BMCTR collect Information about the throughput of the target processor They count for certain events like interrupts cache misses or cpu cycles This information may be helpful in finding bottlenecks and tuning the application Format TrOnchip ATOB ON OFF Format TrOnchip BMCTR0 BMCTR1 bmctr bmctr OFF CMISS INST P...

Page 62: ...f an instruction not being available in the instruction pipeline e g if the pipeline is flushed after a conditional branch or a cache miss on the instruction cache DataNULL Count cycles which have to be inserted because of data not being available Data NULL e g when reading data from a slow off chip memory IDLE If the cpu is in IDLE state this option will count the clock cycles as long as the cpu ...

Page 63: ... this scenario one counter may measure the elapsed time and the second counts for the interrupts which occurred during that time frame In this case both counters are used as 16 bit counters Therefore they may overrun shortly For this reason the benchmark counter can only be applied to short program sections or single functions TrOnchip RESet Reset the TrOnchip settings TrOnchip view Display the Tr...

Page 64: ...s TrOnchip view Display the TrOnchip window TrOnchip BMCTR0 TIME Set the first BMCTR0 benchmark counter to measure the time TrOnchip CLOCK 12 MHz Set the frequency of the CPU Go sieve Go to the function sieve TrOnchip BMCTR0 Init Initialize the benchmark counter Go Return Go to the last instruction of the function sieve TrOnchip RESet Reset the TrOnchip settings TrOnchip view Display the TrOnchip ...

Page 65: ...er optimization TrOnchip DualAccess AET trigger optimization Default ON Supports AET trigger optimization TrOnchip PROfile Display the benchmark data Displays the collected data of the first benchmark counter BMCTR0 in a graphical representation In order to specify a vertical scaling use the optional value parameter Format TrOnchip CLOCK value TrOnchip CLOCK 30 MHz Set the frequency of the cpu For...

Page 66: ...C5000 Debugger 66 1989 2022 Lauterbach TrOnchip RESet Set on chip trigger to default state Sets the TrOnchip settings and trigger module to the default settings Format TrOnchip RESet ...

Page 67: ...ardware setup refer to the AutoFocus User s Guide autofocus_user pdf Controlling the Trace Capture On the C5x cores the trace capture setup is controlled by the AET command group Trace Breakpoints The following breakpoint examples use AET resources Broadcast only the execution of the instruction at address 0x4dd84 Broadcast only the execution of the specified instructions Break Set address range P...

Page 68: ...is a standard 20 pin double row connector pin to pin spacing 0 100 in We strongly recommend to use a connector on your target with housing and having a center polarization e g AMP 2 827745 0 A connection the other way around indeed causes damage to the output driver of the debugger Signal Pin Pin Signal VREF DEBUG 1 2 VSUPPLY not used TRST 3 4 GND TDI 5 6 GND TMS TMSC SWDIO 7 8 GND TCK TCKC SWCLK ...

Page 69: ... input It is connected to the supply translating transceiver nSRST nRESET is used by the debugger to reset the target CPU or to detect a reset on the target It is driven by an open collector buffer A 47 k pull up resistor is included in the ICD AICD connector The debugger will only assert a pulse on nSRST when the SYStem UP the SYStem Mode Go or the SYStem RESetOUT command is executed If it is ens...

Page 70: ...esistor in the ICD connector In environments where multiple tools can access the JTAG port it is absolutely required that there is a pull down resistor at TCK This is to ensure that TCK is low during a hand over between different tools TDO is ICD input only and needs standard TTL level VCCS is used as a sense line for the target voltage It is also used as supply voltage for the output driver of th...

Page 71: ...signs Our debuggers are not supplied with this connector but an adapter is available LA 7748 JTAG ARM Converter ARM TI This is a standard 14 pin double row two rows of seven pins connector pin to pin spacing 0 100 in FAQ Please refer to our Frequently Asked Questions page on the Lauterbach website TMS 1 nTRST TDI GND VTREF GND TDO GND RTCK GND TCK GND EMU0 EMU1 ...

Page 72: ...C5000 Debugger 72 1989 2022 Lauterbach Operation Voltage Adapter OrderNo Voltage Range JTAG Debugger for C5500 ICD LA 7830 1 8 3 6 V ...

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