C5000 Debugger | 21
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1989-2022
Lauterbach
CORE
<core> <chip>
(cont.)
For cores on the same
<chip>,
the debugger assumes that the
cores share the same resource if the control registers of the
resource have the same address.
Default:
<core>
depends on CPU selection, usually 1.
<chip>
derived from
CORE=
parameter in the configuration file
(config.t32), usually 1. If you start multiple debugger instances with
the help of t32start.exe, you will get ascending values (1, 2, 3,...).
CoreNumber
<number>
Number of cores to be considered in an SMP (symmetric
multiprocessing) debug session. There are core types which can
be used as a single core processor or as a scalable multicore
processor of the same type. If you intend to debug more than one
such core in an SMP debug session you need to specify the
number of cores you intend to debug.
Default: 1.
DEBUGPORT
[
DebugCable0
|
DebugCa-
bleA
|
DebugCableB
]
It specifies which probe cable shall be used e.g. “DebugCableA” or
“DebugCableB”. At the moment only the CombiProbe allows to
connect more than one probe cable.
Default: depends on detection.
DEBUGPORTTYPE
[
JTAG
|
SWD
|
CJTAG
|
CJTAGSWD
]
It specifies the used debug port type “JTAG”, “SWD”, “CJTAG”,
“CJTAG-SWD”. It assumes the selected type is supported by the
target.
Default: JTAG.
What is NIDnT?
NIDnT is an acronym for “Narrow Interface for Debug and Test”.
NIDnT is a standard from the MIPI Alliance, which defines how to
reuse the pins of an existing interface (like for example a microSD
card interface) as a debug and test interface.
To support the NIDnT standard in different implementations,
TRACE32 has several special options:
Slave
[
ON
|
OFF
]
If several debuggers share the same debug port, all except one
must have this option active.
JTAG: Only one debugger - the “master” - is allowed to control the
signals nTRST and nSRST (nRESET). The other debuggers need
to have the setting
Slave ON
.
Default: OFF.
Default: ON if
CORE=
... >1 in the configuration file (e.g. config.t32).
