C5000 Debugger | 29
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Lauterbach
<parameters> configuring a CoreSight Debug Access Port “AP”
An Access Port (AP) is a CoreSight module from Arm which provides access via its debug link (JTAG,
cJTAG, SWD, SWD, USB, UDP/TCP-IP, GTL, PCIe...) to:
1.
Different memory busses (AHB, APB, AXI). This is especially important if the on-chip debug
register needs to be accessed this way. You can access the memory buses by using certain
access classes with the debugger commands: “AHB:”, “APB:”, “AXI:, “DAP”, “E:”. The interface to
these buses is called Memory Access Port (MEM-AP).
2.
Other, chip-internal JTAG interfaces. This is especially important if the core you intend to debug
is connected to such an internal JTAG interface. The module controlling these JTAG interfaces is
called JTAG Access Port (JTAG-AP). Each JTAG-AP can control up to 8 internal JTAG interfaces.
A port number between 0 and 7 denotes the JTAG interfaces to be addressed.
3.
A transactor name for virtual connections to AMBA bus level transactors can be configured by
the property
SYStem.CONFIG.*APn.XtorName
<name>
. A JTAG or SWD transactor must be
configured for virtual connections to use the property “Port” or “Base” (with “DP:” access) in case
XtorName remains empty.
Example 1
: SoC-400
SoC-400
Memory
Access Port
(MEM-AP)
Debug
Port
(DP)
Memory
Access Port
(MEM-AP)
JTAG
Access Port
(JTAG-AP)
CoreSight
Component
ROM table
ROM table
CoreSight
Component
DAP
