15-4
LatticeECP2/M sysCONFIG Usage Guide
DONE
The DONE pin is a dedicated bi-directional open drain with a weak pull-up (default), or it is an actively driven pin.
DONE goes low when INITN goes low, when INITN and PROGRAMN go high, and the internal Done bit is pro-
grammed at the end of configuration, the DONE pin will be released (or driven high, if it is an actively driven pin).
The DONE pin can be held low externally and, depending on the wake-up sequence selected, the device will not
become functional until the DONE pin is externally brought high. Externally delaying the wake-up sequence using
the DONE pin is a good way to synchronize the wake-up of multiple FPGAs; it is also required when configuring
multiple FPGAs from a single configuration device.
Sampling the DONE pin is a good way for an external device to tell if the FPGA has finished configuration. How-
ever, when using IEEE 1532 JTAG to configure SRAM the DONE pin is driven by a boundary scan cell, so the state
of the DONE pin has no meaning during IEEE 1532 JTAG configuration (once configuration is complete, DONE
reverts to internal logic and will be high).
CCLK
CCLK is a dedicated bi-directional pin; direction depends on whether a Master or Slave mode is selected. If a Mas-
ter mode (SPI or SPIm) is selected, via the CFG pins, the CCLK pin becomes an output; otherwise CCLK is an
input.
If the CCLK pin becomes an output, the internal programmable oscillator is connected to CCLK and is driven out to
slave devices. CCLK will stop 120 clock cycles after the DONE pin is brought high. The extra clock cycles ensure
that enough clocks are provided to wake-up other devices in the chain. When stopped, CCLK becomes an input
(tri-stated output). CCLK will restart (become an output again) on the next configuration initialization sequence.
The MCCLK_FREQ parameter (one of the global preferences in the Design Planner of ispLEVER or the Spread-
sheet View in Diamond) controls the CCLK master frequency (see data sheet On-Chip Oscillator section for the fre-
quency selection). The software default setting for the configuration CCLK is 2.5 MHz. For a complete list of the
supported Master Clock frequencies, please see the
LatticeECP2/M Family Data Sheet
. One of the first operations
during configuration is the MCCLK_FREQ parameter; once this parameter is loaded the frequency changes to the
selected value. Care should be exercised not to exceed the frequency specification of the slave devices or the sig-
nal integrity capabilities of the PCB layout.
When downloading an encrypted bitstream file to the LatticeECP2/M S-Series devices, the user must adhere to the
appropriate conditions for the CCLK signal. These conditions are shown in TN1109,
Dual-Purpose sysCONFIG Pins
The following is a list of the dual-purpose sysCONFIG pins. If any of these pins are used for configuration and for
user I/O, the user must adhere to the requirements listed at the start of the Configuration pin sections. On
LatticeECP2M50/M70/M100 devices, the sysCONFIG pins described below are dedicated pins. When using the
same pins to access the external boot Flash, the system design must take care of tri-stating these output pins while
driving these pins from a different I/O pin.
These pins are powered by V
CCIO8
.
DI/CSSPI0N
The DI/CSSPI0N dual-purpose pin is designated as DI (Data Input) for Serial configurations. DI has an internal
weak pull-up. DI captures data on the rising edge of CCLK.
In SPI or SPIm mode the DI/CSSPI0N becomes a low true Chip Select output that drives the SPI Serial Flash chip
select.
DOUT/CSON
The DOUT/CSON pin is an output pin and has two purposes.
