15-3
LatticeECP2/M sysCONFIG Usage Guide
Dedicated Control Pins
The following sub-sections describe the LatticeECP2/M dedicated sysCONFIG pins. These pins are powered by
V
CCIO8
.
While the device is under IEEE 1149.1 or 1532 JTAG control the dedicated programming pins have no meaning.
This is because a boundary scan cell will control each pin, per JTAG 1149.1, rather than normal internal logic.
CFG[2:0]
The Configuration Mode pins, CFG[2:0], are dedicated inputs with weak pull-ups. The CFG pins are sampled on
the rising edge of INITN and are used to select the configuration mode, i.e. what type of device the LatticeECP2/M
will configure from. As a consequence the CFG pins determine which groups of dual-purpose pins will be used for
device configuration (see the right-most column in Table 15-2). See Table 15-3 for a list of Configuration Modes.
Table 15-3. Configuration Modes
PROGRAMN
The PROGRAMN pin is a dedicated input with a weak pull-up. This pin is used to initiate a non-JTAG SRAM config-
uration sequence.
A high to low signal applied to PROGRAMN takes the device out of user mode and sets it into configuration mode.
The low to high transition will initiate the configuration process. The PROGRAMN pin can be used to trigger config-
uration at any time.
INITN
The INITN pin is a bidirectional open drain control pin. INITN is capable of driving a low pulse out as well as detect-
ing a low pulse driven in.
When the PROGRAMN pin is driven low, or a JTAG Reset instruction is received, or after the internal Power-On-
Reset signal is released during power-up, the INITN pin will be driven low to reset the internal configuration cir-
cuitry. Once the PROGRAMN pin is driven high, the configuration initialization begins. Once the configuration ini-
tialization is completed, the INITN pin will go high. To delay configuration the INITN pin can be held low externally.
The device will not enter configuration mode as long as the INITN pin is held low. A low to high transition on INITN
causes the CFG pins to be sampled, telling the LatticeECP2/M which port to use, and starts configuration.
During configuration the INITN pin becomes an error detection pin. If a CRC error is detected during configuration
INITN will be driven low. The error will be cleared at the beginning of the next configuration.
Configuration Mode
CFG[2]
CFG[1]
CFG[0]
D[0]/SPIFASTN
SPI
Normal (0x03)
0
0
0
Pull-Up
Fast (0x0B)
0
0
0
Pull-Down
Reserved
0
0
1
X
SPIm
Normal (0x03)
0
1
0
Pull-Up
Fast (0x0B)
0
1
0
Pull-Down
Reserved
0
1
1
X
Reserved
1
0
0
X
Slave Serial
1
0
1
X
Reserved
1
1
0
X
Slave Parallel
1
1
1
D0
Notes:
JTAG is always available for IEEE 1149.1 and 1532 support.
