15-5
LatticeECP2/M sysCONFIG Usage Guide
For serial and parallel configuration modes, when BYPASS mode is selected, this pin becomes DOUT (see
Figure 15-9). When the device is fully configured a Bypass instruction in the bitstream is executed and the data on
DI, or D[0:7] in the case of a parallel configuration mode, will then be routed to the DOUT pin. This allows data to
be passed, serially, to the next device. In a parallel configuration mode D0 will be shifted out first followed by D1,
D2, and so on.
For parallel configuration mode there is a Flowthrough option as well. When Flowthrough mode is selected this pin
becomes Chip Select Out (CSON). When the device is fully configured, and the Flowthrough instruction in the bit-
stream is executed, the CSON pin is driven low to enable the next device. The data pins, D[0:7], are wired in paral-
lel to each device in the chain (see Figure 15-10).
In SPIm mode, the sysCONFIG daisy chaining mode of configuration is not supported.
The DOUT/CSON drives out a high on power-up and will continue to do so until the execution of the Bypass/Flow
Through instruction within the bitstream, or until the I/O Type is changed by the user code.
CSN and CS1N
Both CSN and CS1N are active low input pins with weak pull-ups and are used in parallel mode only. These inputs
are OR’ed and used to enable the D[0:7] data pins to receive or output a byte of data.
Note: In the 144-pin TQFP
and 208-pin PQFP packages, CSN, CS1N and WRITEN are not bonded out.
When CSN or CS1N is high, the D[0:7], and BUSY pins are tri-stated. CSN and CS1N are interchangeable when
controlling the D[0:7], and BUSY pins. Driving both CSN and CS1N high causes the LatticeECP2/M to exit Bypass
or Flowthrough mode and resets the Bypass register. If Bypass or Flowthrough mode will not be used then CSN or
CS1N may be tied low, i.e. in this case it is only required that one of these pins be driven. The CSN and CS1N pins
must remain low while the configuration bitstream is being sent to the device or the configuration will fail.
If SRAM (configuration memory) needs to be accessed using the parallel pins while the part is in user mode (the
DONE pin is high) then the PERSISTENT preference must be set to ON to preserve these pins as CSN and CS1N.
CSN and CS1N are not connected in the 100-pin TQFP and 208-pin PQFP devices. Note that SRAM may only be
read using JTAG or Slave Parallel mode.
WRITEN
The WRITEN pin is an active low input with a weak pull-up and used for parallel mode only.
Note: In the 144-pin
TQFP and 208-pin PQFP packages, CSN, CS1N and WRITEN are not bonded out.
The WRITEN pin is used to determine the direction of the data pins D[0:7]. The WRITEN pin must be driven low in
order to clock a byte of data into the device and driven high to clock data out of the device.
If SRAM (configuration memory) needs to be accessed using the parallel pins while the part is in user mode (the
DONE pin is high) then the PERSISTENT preference must be set to ON to preserve this pin as WRITEN. WRITEN
is not connected in the 100-pin TQFP and 208-pin PQFP devices. Note that SRAM may only be read using JTAG or
Slave Parallel mode.
BUSY/SISPI
The BUSY/SISPI pin has two functions.
In parallel configuration mode, the BUSY pin is a tri-stated output. The BUSY pin will be driven low by the device
only when it is ready to receive a byte of data on D[0:7] or a byte of data is ready for reading. The BUSY pin allows
the LatticeECP2/M to pause transfers on the parallel port.
If SRAM (configuration memory) needs to be accessed using the parallel pins while the part is in user mode (the
DONE pin is high) then the PERSISTENT preference must be set to ON to preserve this pin as BUSY. Note that
SRAM may only be read using JTAG or Slave Parallel mode.
In SPI or SPIm configuration modes, the BUSY/SISPI pin becomes an output that drives control and data to the
SPI Serial Flash. Control and data are output on the falling edge of CCLK. If SPI memory needs to be accessed
