MachXO2 Programming and Configuration Usage Guide
38
Wake-up Clock Selection
The clock source used to complete the four state transitions in the wake-up sequence is user-selectable. Once the
MachXO2 is configured, it enters the wake-up state, which is the transition between the configuration mode and
user mode. This sequence is synchronized to a clock source, which defaults to MCLK/CCLK when sysCONFIG is
used, or TCK when JTAG is used.
You can change the clock used by instantiating the START macro in your Verilog or VHDL. The clock must be sup-
plied on an external input pin, because the MachXO2 does not begin internal operations until the Wake-up
sequence is complete. There is no external indication the device is ready to perform the last four state transitions.
You must either provide a free running clock frequency, or you must wait until the device is guaranteed to be ready
to wake up. Using the START macro provides another mechanism for holding off configuring one or more program-
mable devices and then starting them synchronously.
Verilog
module START (STARTCLK);
input STARTCLK;
endmodule
START u1 (.STARTCLK(<clock_name>)) /* synthesis syn_noprune=1 */;
VHDL
COMPONENT START
PORT(
STARTCLK : IN STD_ULOGIC
);
END COMPONENT;
attribute syn_noprune: boolean ;
attribute syn_noprune of START: component is true;
begin
u1: START port map (STARTCLK =><clock name>);
