MachXO2 Programming and Configuration Usage Guide
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has a minimum pulse width assertion period in order for it to be recognized by the FPGA. You can find this mini-
mum time in DS1035,
in the AC timing section.
Be aware of the following special cases when the PROGRAMN pin is active:
• If the device is currently being programmed via JTAG then PROGRAMN will be ignored until the JTAG mode pro-
gramming sequence is complete.
• Toggling the PROGRAMN pin during device configuration will interrupt the process and restart the configuration
cycle. Please keep PROGRAMN pin de-asserted (held High) during device configuration.
• Asserting PROGRAMN on a device in Feature Row HW Default Mode state disables the SSPI and I
2
C ports.
Start SSPI or I
2
C programming operations after PROGRAMN is deasserted.
• PROGRAMN is active during power-up, even when PROGRAMN has been reserved as a general purpose I/O.
Do not allow any input signal attached to PROGRAMN to transition from high to low at a frequency greater than
the VCC (min) to INITN rising edge time period. High to low PROGRAMN assertions more frequently prevent the
MachXO2 from configuring, causing the FPGA to remain in a continuous RESET condition. See Figure 5.
• PROGRAMN must be deasserted, even if recovered for GPIO, whenever the Feature Row is erased or re-pro-
grammed. If asserted, configuration may not complete successfully.
Figure 5. Period PROGRAMN is Always Observed
Figure 6. Configuration from PROGRAMN Timing
INITN: The INITn pin is a bidirectional open-drain control pin. It has the following functions:
• After power is applied, after a PROGRAMN assertion, or a REFRESH command it goes low to indicate the
SRAM configuration memory is being erased. The low time assertion is specified with the t
INTIL
parameter.
• After the t
INTIL
time period has elapsed the INITn pin is deasserted (i.e. is active high) to indicate the MachXO2
is ready for its configuration bits. The MachXO2 begins loading configuration data from either the internal Flash
memory or an external SPI Flash.
• INITn can be asserted low by an external agent before the t
INTIL
time period has elapsed in order to prevent the
FPGA from reading configuration bits. This is useful when there are multiple programmable devices chained
together. The programmable device with the longest t
INTIL
time can hold all other devices in the chain from start-
ing to get data until it is ready itself.
PROGRAMN
INITN
VCC
VCC min.
PROGRAMN transitions observed
DONE
INITN
PROGRAMN
t
PRGMJ
t
INITL
t
DPPINIT
t
DPPDONE
