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Lattice Semiconductor MachXO2 Series, Programming And Configuration Usage Manual

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Lattice Semiconductor MachXO2 Series Programming And Configuration Usage Manual Download Page 17

MachXO2 Programming and Configuration Usage Guide

17

CSSPIN pin is asserted to the attached SPI Flash. The MachXO2 asserts CSSPIN until all configuration data bytes 
have been loaded, at which time the CSSPIN enters a high impedance state. 

When the MachXO2 is in the Feature Row HW Default Mode state the CSSPIN is a general purpose I/O with a 
weak pulldown. It must have an external pullup resistor when the External and Dual Boot configuration modes are 
used. CSSPIN must ramp in tandem with the SPI PROM VCC input. It remains a general purpose I/O when the 
FPGA enters user mode. You must ENABLE the Master SPI port to reserve CSSPIN for use by the internal SPI 
Master logic.

When configuring from an external SPI Flash, ensure that the SPI Flash V

CC

 and the MachXO2 V

CCIO2

 are at the 

same level. Ensure that the SPI Flash V

CC

 meets is at the recommended operating level. 

Some SPI PROM manufacturers require the chip select input of the PROM ramp in unison to the PROMs VCC rail. 
The CSSPIN pin, by default, has a weak pull-down resistor internally. Adding a 4.7 kOhm to 10 kOhm pull-up resis-
tor to the CSSPIN pin on the MachXO2 is recommended. 

SI/SISPI: The SI/SISPI is a dual function bi-directional pin. The direction depends upon whether a Master or Slave 
mode is active. The SI/SISPI is an input data pin when using the Slave SPI mode and is an output data pin when 
using the Master SPI mode. In Master SPI mode, the MachXO2 drives SI/SISPI until all configuration data bytes 
have been loaded, at which time the SI/SISPI enters a high impedance state. 

At least one of the sysCONFIG preferences, SLAVE_SPI_PORT or MASTER_SPI_PORT, must be set to ENABLE 
in order to preserve this pin as SI/SISPI and allow access to the SPI interface. 

SO/SPISO: The SO/SPISO pin is a dual function bi-directional pin. The direction depends upon whether a Master 
or Slave mode is active. The SO/SPISO is an input data pin when using the Master SPI mode and is an output data 
pin when using the Slave SPI mode.

At least one of the sysCONFIG preferences, SLAVE_SPI_PORT or MASTER_SPI_PORT, must be set to ENABLE 
in order to preserve this pin as SO/SPISO and allow access to the SPI interface. 

I

2

C Configuration Port Pins

SCL: The MachXO2 provides an I

2

C configuration port. The SCL is the I

2

C Serial Clock pin, and is used to initiate 

and time transactions on the I

2

C bus. It is a bi-directional, open-drain signal that is an output when the MachXO2 

I

2

C controller is mastering transactions on the bus, and is an input when an external I

2

C master is accessing 

resources inside the MachXO2. SCL requires an external pull-up resistor in order to operate.

The SCL pin is available when the MachXO2 is in the Feature Row HW Default Mode state. You must ENABLE the 
I2C_PORT and instantiate the Embedded Function Block (EFB) for the I

2

C port to continue to be available in user 

mode (see the 

I2C Configuration Mode

 section for details.) The SCL pin becomes a general purpose I/O if you do 

not ENABLE the I2C_PORT.

SDA: The SDA pin is the I

2

C serial data input/output pin. It is bi-directional, open-drain, and requires an external 

pull-up resistor in order to operate. The pin changes direction dynamically during data transactions on the I

2

C bus. 

The current state depends on the current bus master and the operation being performed by that master. 

The SDA pin is available when the MachXO2 is in the Feature Row HW Default Mode state. You must ENABLE the 
I2C_PORT and instantiate the EFB if you want the I

2

C port to continue to be available in user mode (see the 

I2C 

Configuration Mode

 section for details.) The SDA pin becomes a general purpose I/O if you do not ENABLE the 

I2C_PORT. 

JTAG Configuration Port Pins

The JTAG pins provide a standard IEEE 1149.1 Test Access Port (TAP). The JTAG port is the only configuration 
port on the MachXO2 that is capable of performing configuration, programming, and multi-device configuration 
functions. Programming and configuration over the JTAG port uses IEEE 1532 compliant commands. In addition to 
the IEEE 1532 capabilities, the MachXO2 provides all of the mandatory IEEE 1149.1 Test Access Port commands 
allowing printed circuit board assembly verification. 

Summary of Contents for MachXO2 Series

Page 1: ...ns available to you for building the programming solution that fits your needs Each of the options available will be described in detail so that you can put together the pro gramming and configuration solution that meets your needs MachXO2 Features Key programming and configuration features of MachXO2 devices are Instant on configuration from internal Flash PROM powers up in milliseconds Single ch...

Page 2: ...line mode programming configuration the FPGA no longer operates in user mode The contents of the non volatile or SRAM configuration memory are updated but the MachXO2 does not perform your logic operations until offline mode programming configuration is complete Number Formats The following nomenclature is used to denote the radix of numbers 0x Numbers preceded by 0x are hexadecimal b suffix Numbe...

Page 3: ... configuration port does not have the ability to alter the Flash mem ory space and as a result is not a factor in the sysCONFIG port priority scheme The priority scheme is important to be aware of as a Configuration Logic operation using a low priority sysCONFIG port can be interrupted by a higher priority sysCONFIG port The operation of the Configuration Logic is not defined when a low priority s...

Page 4: ...lear all of the SRAM memory inside the FPGA The FPGA remains in the initialization state until all of the following conditions are met The tINITL time period has elapsed The PROGRAMN pin is deasserted The INITN pin is no longer asserted low by an external master The dedicated INITN pin provides two functions during the initialization phase The first is to indicate the FPGA is currently clearing it...

Page 5: ...OE Global Set Reset GSR Global Write Disable GWDISn External DONE The first phase of the Wake Up process is for the MachXO2 to release the Global Output Enable When it is asserted permits the FPGA s I O to exit a high impedance state and take on their programmed output function The FPGA inputs are always active The input signals are prevented from performing any action on the FPGA flip flops by th...

Page 6: ...the MachXO2 Sending the Refresh command using a configuration port Invoking one of these methods causes the MachXO2 to drive INITN and DONE low The MachXO2 enters the ini tialization state as described earlier Memory Space Accessibility The two internal memories Flash and SRAM of the MachXO2 have the ability to be read and written Each port on the MachXO2 has a different level of access to each me...

Page 7: ...e during background programming The required duration erase portion of the background Flash programming time is specified in Table 97 of TN1246 Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide The left side PLL can stay active during background programming Bitstream PROM Sizes The MachXO2 is a SRAM based FPGA The SRAM configuration memory must be loaded fro...

Page 8: ...Configuration Flash and UFM memory you can store the device bitstream in an external SPI Flash Table 2 shows the maximum uncompressed bitstream sizes allowing you to select a SPI Flash Table 2 Maximum Configuration Bits Device Uncompressed Bitstream Size Without EBR Uncompressed Bitstream Size With EBR Maximum Internal Flash Units LCMXO2 256 0 09 N A 0 071 Mb LCMXO2 256HC 0 09 N A 0 071 Mb LCMXO2 ...

Page 9: ...ur hardware Feature Row can be erased or programmed independently When Feature Row is erased Feature Row sets its value back to HW default mode state Feature Row can be modified using Programming File Utility under Tools Feature Row Editor Figure 4 Feature Row Example A relationship of Feature Row option and Diamond Spreadsheet View is shown in Table 3 and Table 4 Table 3 Feature Row Option and Di...

Page 10: ... and reprogrammed during Flash erase program and verify sequence both offline and online During offline flash programming if you do not want Feature Row to be erased and reprogrammed Lattice recommends that you use XFLASH Erase Program Verify Refresh operation Feature Row settings can be altered using the Diamond Spreadsheet View Spreadsheet View allows you to edit the configuration settings for t...

Page 11: ...mming of the internal memory usu ally as a result of a loss of power is the primary reason MachXO2 would fail to configure The JTAG port s advantage is that it provides the widest set of functions and features for programming configuring and testing the MachXO2 system sysCONFIG Ports Table 6 MachXO2 Programming and Configuration Ports sysCONFIG Pins The MachXO2 provides a set of sysCONFIG I O pins...

Page 12: ...sCONFIG Pins1 Table 8 Default State in Diamond for Each Port Self Download Port Pins PROGRAMN The PROGRAMN is an input used to configure the FPGA The PROGRAMN pin when enabled is sensitive to a high to low transition and has an internal weak pull up When PROGRAMN is asserted low the FPGA exits user mode and starts a device configuration sequence at the Initialization phase as described earlier Hol...

Page 13: ... the FPGA to remain in a continuous RESET condition See Figure 5 PROGRAMN must be deasserted even if recovered for GPIO whenever the Feature Row is erased or re pro grammed If asserted configuration may not complete successfully Figure 5 Period PROGRAMN is Always Observed Figure 6 Configuration from PROGRAMN Timing INITN The INITn pin is a bidirectional open drain control pin It has the following ...

Page 14: ...DONE bit will not be set the DONE pin will stay low and the device will not wake up The device will fail configuration when the following hap pens The bitstream CRC error is detected The invalid command error detected A time out error is encountered when loading from the on chip Flash The program done command is not received when the end of on chip SRAM configuration or on chip Flash memory is rea...

Page 15: ...LK This allows an external Slave SPI master controller to program the MachXO2 The maximum CCLK frequency and the data setup hold parameters can be found in the AC timing section of DS1035 MachXO2 Family Data Sheet The Feature Row must be configured to ENABLE the Slave SPI Port if you want to use the port to reprogram the MachXO2 after it enters user mode The MCLK CCLK pin functions as a Master Clo...

Page 16: ...t Mode state and in user mode when the Slave SPI port is set to the ENABLE setting The SN pin is a general purpose I O in user mode when the Slave SPI port is set to the DISABLE setting Proper operation of the MachXO2 depends upon maintaining the SN pin in the correct state SN must be deasserted that is held High when configuring using Master SPI mode SN signal needs to be clean during power up No...

Page 17: ... mode At least one of the sysCONFIG preferences SLAVE_SPI_PORT or MASTER_SPI_PORT must be set to ENABLE in order to preserve this pin as SO SPISO and allow access to the SPI interface I2 C Configuration Port Pins SCL The MachXO2 provides an I2 C configuration port The SCL is the I2 C Serial Clock pin and is used to initiate and time transactions on the I2 C bus It is a bi directional open drain si...

Page 18: ...up to VCCIO Bank 0 TDI The Test Data Input TDI pin is used to shift in serial test instructions and data This pin should be wired to TDI of the JTAG connector or to TDO of an upstream device in a JTAG chain An internal pull up resistor on the TDI pin is provided The internal resistor is pulled up to VCCIO of Bank 0 TMS The Test Mode Select TMS pin is an input pin that controls the progression thro...

Page 19: ...ation Modes The MachXO2 provides multiple options for loading the configuration SRAM from a non volatile memory The previ ous section described the physical interface necessary to interact with the MachXO2 configuration logic This sec tion focuses on describing the functionality of each of the different configuration modes Descriptions of important settings required in the Diamond Spreadsheet View...

Page 20: ...s CONFIGURATION entry The default state for the CONFIGURATION entry is to be set to CFG The configuration data can be logically split to place the pre initialization data for the EBR into the UFM Setting the CONFIGURATION option to CFG_EBRUFM causes the Diamond software to place the configuration data into the Configuration Flash and the EBR initialization data into the UFM This locates the EBR in...

Page 21: ...lied a REFRESH com mand is received or the PROGRAMN pin is asserted and released The MCLK CCLK I O takes on the Master Clock MCLK function and begins driving a nominal 2 08 MHz clock to the SPI Flash s SCLK input CSSPIN is asserted low commands are transmitted to the PROM over the SI SISPI output and data is read from the PROM on the SO SPISO input pin When all of the configuration data is retriev...

Page 22: ...ransfer a configuration data file from your personal computer This is useful during board development and debug Note To support JTAG to MSPI passthru programming mode a 1Kohm pull up resister is required on MCLK Another way to program a SPI Flash using the JTAG port is to use the Lattice ispVME solution ispVME is C code written for an embedded microprocessor The microprocessor reads a data file cr...

Page 23: ...ory A time out error is encountered when loading from on chip Flash A CRC error is caused by incorrect data being written into the internal Flash memory Data is read from the Flash memory in rows As each row enters the Configuration Engine the data is checked for CRC consistency Before the data enters the Configuration SRAM the CRC must be correct Any incorrect CRC causes the device to erase the C...

Page 24: ...red at offset 0x000000 The following are the recommended processes for programming internal and external flash to use Dual Boot Mode Option A Using background mode to program external flash 1 Program MachXO2 internal flash using Flash Programming Mode Make sure SPI port enabled and per sistent on 2 Program the external SPI flash in background mode 3 Refresh or power cycle Option B Using offline mo...

Page 25: ...l erasure of the Feature Row it is recommended the SSPI port be used to perform transparent updates of the Flash memory The SSPI port can issue a REFRESH command to make a newly programmed image active The REFRESH command can be safely used when the MachXO2 is using External or Dual Boot configuration mode because the REFRESH opera tion will not begin until SN is deasserted Programming the MachXO2...

Page 26: ...disabling the I2 C port Figure 13 I2 C Configuration Logic There are two hardened I2 C controllers in a MachXO2 device a primary and a secondary The primary controller provides an interface to the MachXO2 Configuration Logic and access to Wishbone registers Access to the Wish bone registers is referred to as User Mode I2 C The primary I2 C controller is the only one that permits access to the Conf...

Page 27: ... configuration logic to respond with data In the event that the I2 C memory transaction is interrupted or abandoned the configuration logic continues to return the queued data New incoming I2 C com mands may be considered padding bytes or may be misinterpreted Clear this condition by writing any value to off set 3 The configuration logic command interpreter will reset any queued data will be flush...

Page 28: ...TAG port pins for use as general purpose I O The MachXO2 JTAG port is a valuable asset due to its flexibility It provides the best capabilities for system and device debug Lattice recommends the JTAG port remain accessible in every MachXO2 design Advantages for keeping the JTAG port active include Multi chain Architectures The JTAG port is the only configuration and programming port that permits t...

Page 29: ... Reset Configuration SRAM Flash with Golden Image System running Program SPI PROM with new pattern 1 Halt sys clk Issue TransFR Refresh instruction through JTAG 3 System running again with new image4 Release sys clock Global Reset occurs Program MachXO2 Feature Row to Dual Boot through JTAG 2 5 Assume MachXO2 Flash has been programmed and running Can use Diamond Programmer Notes 1 User can use ope...

Page 30: ... reset option so that when GSR occurs the state of the I O pin will not trigger a system crash Software Selectable Options The operation of the MachXO2 configuration logic is managed by options selected in the Diamond design software Other FPGAs provide dedicated I O pins to select the configuration mode The MachXO2 uses the non volatile Feature Row to select how it will configure The Feature Row ...

Page 31: ...ow is erased The only exception is the MCCLK_FREQ parameter which is stored in the configuration data The configuration and port options can be used in any combination Table 18 Configuration Mode Port Options Option Name Default Setting All Settings JTAG_PORT ENABLE DISABLE ENABLE SLAVE_SPI_PORT DISABLE DISABLE ENABLE MASTER_SPI_PORT DISABLE DISABLE ENABLE EFB_USR I2C_PORT DISABLE DISABLE ENABLE S...

Page 32: ...the MASTER_SPI_PORT It is necessary to guaran tee that the internal SPI master controller not perform SPI transactions at the same time as an external SPI master It is your responsibility to prevent two SPI masters from operating simultaneously Master SPI Port The MASTER_SPI_PORT allows you to preserve the SPI configuration port after the MachXO2 device enters user mode There are three states to w...

Page 33: ...RAM DONE and INITN in user mode Lattice recommends setting the SDM_PORT to PROGRAMN when using Master SPI or Dual Boot configuration modes The PROGRAMN pin is the only way to perform a warm reconfiguration of the MachXO2 device unless another configuration port is available to transmit a REFRESH command MCCLK Frequency The MCLK_FREQ preference allows you to alter the MCLK frequency used to retriev...

Page 34: ...This preference creates configuration data that is stored in the Configuration Flash This mode dif fers from CFG by allowing the configuration data to overflow into the UFM The configuration data increases in size as EBR initialization data is added to the design EXTERNAL This preference generates configuration data that is stored in an external memory The UFM sec tor is available as general purpo...

Page 35: ...e See the MY_ASSP section for more information about how to assign a value to the CUSTOM_IDCODE preference CUSTOM_IDCODE_FORMAT The CUSTOM_IDCODE_FORMAT preference selects the format for the data field used to assign a value in the CUSTOM_IDCODE preference The CUSTOM_IDCODE_FORMAT has two options Binary CUSTOM_IDCODE is set using 32 1 or 0 characters Hex CUSTOM_IDCODE is set using eight hexadecima...

Page 36: ...ge the value returned when the IDCODE is read from the FPGA Set the MY_ASSP preference to the ON state Turning the MY_ASSP ON enables the CUSTOM_IDCODE prefer ence CUSTOM_IDCODE The CUSTOM_IDCODE is the value you assign to override the default IDCODE in the MachXO2 device You are only allowed to enter a 32 bit hexadecimal or binary value when the MY_ASSP preference is ON Overriding the IDCODE prev...

Page 37: ...e chain or the last device in a chain the wake up process should be initiated by the completion of configuration Once configuration is complete the internal DONE bit will be set and then the wake up process will begin Figure 18 shows the wake up sequence using the internal clock Figure 18 Wake up Sequence Using Internal Clock Wake up Signals Three internal signals GSR GWDIS and GOE determine the w...

Page 38: ...nput pin because the MachXO2 does not begin internal operations until the Wake up sequence is complete There is no external indication the device is ready to perform the last four state transitions You must either provide a free running clock frequency or you must wait until the device is guaranteed to be ready to wake up Using the START macro provides another mechanism for holding off configuring...

Page 39: ...rent programming modes to erase program and verify the MachXO2 Flash memory resources The WISHBONE interface is only permitted to use transparent programming operations The sequence and timing of the commands presented to the Configuration Logic are identical across all of the configuration ports There are slight differences due to communication protocol standards when transmit ting commands and d...

Page 40: ...he header which does not have an identifier to indicate its start Only ASCII characters are legal after B The header is terminated by an asterisk character Field Terminator Each field in the JEDEC file will be terminated with an asterisk Note Comment NOTE my design The key word N marks the beginning of the comment It can appear any where in the JEDEC file Lattice s JEDEC files add OTE to the N key...

Page 41: ...t necessary to program any page data containing all 0 values UFM pages if present in the JEDEC are preceded by a NOTE TAG DATA line If the JEDEC file is encrypted all the data in the link field are encrypted The column size will increase accordingly to include filler bits to make the column size packet 128 bit or 16 bytes per packet bounded Fuse Checksum CC1B9 The checksum of all the fuses Fuse co...

Page 42: ...101111111010111010101111101111000101000100 00100010000000000000000000000000110000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111 NOTE EBR_INIT DATA L137984 11111111111111111111111111111111111101100000000000000000000000000000000000000000000110000000000010110010000100000000000010000000 000111101000111101000111101000111101000111101000111101000111101000111101...

Page 43: ...tus Register Command 0x3C Read 32 ID Bits Transmit Enable Configuration Interface Offline Mode Command 0xC6 Transmit Read Busy Flag 0xF0 and Read Status Register Command 0x3C Transmit Read Status Register Command 0x3C Note Do not use fixed delays for the Flash erase sequence No No No No o N o N Yes Yes Yes Yes Yes No Check Flags Delay 5 µs Busy Transmit Read Busy Flag 0xF0 and Read Status Register...

Page 44: ... Yes Yes No Busy Last Row Yes No Yes Yes Program UFM Compare Row Count No No Delay 200 µs Transmit Read Busy Flag or Read Status Register Command Transmit Reset Configuration Address 0x46 or Set Address Command 0xB4 Transmit Reset UFM Address 0x46 or Set Address Command 0xB4 Program Configuration Flash No 1 2 ...

Page 45: ...rify Usercode Transmit Read Status Register Command 0x3C Usercode OK Transmit Read USER CODE Command 0xC0 Yes Yes Check Busy Yes No Busy Yes No Delay 200 µs Transmit Read Busy Flag 0xF0 or Read Status Register Command 0x3C No Verify Configuration Flash Yes Transmit Reset Config uration Address 0x46 or Set Flash Address Command 0xB4 Contined on Next Page 2 3 ...

Page 46: ...Command with Number of Pages 0x73 Continued from Previous Page Program Done No Transmit Write Feature Row Command 0xE4 Write Feature Row Yes Clean Up No Feature Row OK Transmit Read Feature Row Command 0xE7 Transmit Write FEABITS Command 0xF8 Yes Check Busy Yes No Busy Yes No Delay 200 µs Transmit Read Busy Flag 0xF0 or Read Status Register Command 0x3C 3 4 Program Done Yes Transparent Configurati...

Page 47: ...y Yes Transmit Read Busy Flag 0xF0 or Read Status Register Command 0x3C DONE Set Transmit Read Busy Flag 0xF0 or Read Status Register Command 0x3C Transmit Program DONE Command 0x5E No Transmit Read FEABITS Command 0xFB Transmit Read Status Register Command 0x3C Clean Up No Clean Up Program Done No FEABITS OK Check Busy 4 5 ...

Page 48: ...r Command 0x3C Write Security Bit Yes Yes Check Flags Yes No No Yes Transmit Read OTP Command 0xFA No Busy Program OTP Fuses Verify OTP Fuses OTP Fuses OK Busy Yes Yes Transmit Program SECURITY 0xCE or SECURITY PLUS Command 0xCF Transmit Read Busy Flag 0xF0 or Read Status Register Command 0x3C Delay 200 µs No No Clean Up 5 6 Fail No Exit Yes ...

Page 49: ... Transmit Refresh Command 0x79 No No Yes Yes Yes Offline Mode Transmit Disable Configuration Interface Command 0x26 Wait tREFRESH Done Check for Success Clean Up Exit Transmit Read Status Register Command 0x3C Yes No No Refresh Successful Retry Count Exceeded 6 Refresh Yes To Read Status Register over the I2 C configuration port the MachXO2 must have the EFB instantiated and with the EFB wb_clk_i ...

Page 50: ...ag 0xF0 or Read Status Register Command 0x3C Note Do Not use fixed delays for the Flash erase sequence Note The MachXO2 Configuration Flash UFM Feature Row memories are erased Clean Up Done Transmit Erase Flash CF UFM FR Command 0x0E Transmit Refresh Command 0x79 No Yes Busy ...

Page 51: ...iguration Flash sector Set Address LSC_WRITE_ADDRESS 0xB4 000000 M0 00 PP PP N A Set the Page Address pointer to the Flash page specified by the least significant 14 bits of the PP PP field The M field defines the Flash memory space to access Field 0x0 0x4 M Configuration Flash UFM Program Page LSC_PROG_INCR_NV 0x70 000001 YY 16 N A Program one Flash page Can be used to program the Configuration F...

Page 52: ...ng mode ISC_DISABLE causes the MachXO2 to automatically reconfigure when leaving Offline programming mode Thus when leaving Offline programming mode the Con figuration SRAM must be explicitly cleared using ISC_ERASE 0x0E prior to transmit ting ISC_DISABLE The recommended exit command from Offline programming mode is LSC_REFRESH 0x79 wherein ISC_ERASE and ISC_DISABLE are not necessary See Figure 20...

Page 53: ...can be seen in Figure 22 all interfaces return the page at the Page Address Pointer immediately For single page read operations all configuration ports are allowed to terminate the read immediately following the transfer of the final byte of the first page The I2 C interface differs only in the Read Flash Read UFM Flash operand bytes Reading more than one page requires special handling The multipl...

Page 54: ...d list Added reference to Figure 18 Updated Feature Row section Added footnote 3 in Table 4 MachXO2 Feature Row Elements Updated sysCONFIG Pins section Added footnotes 1 and 2 to Table 7 Default State of the sysCONFIG Pins Updated Figure 9 JTAG Port Behavior with JTAG_PORT DIS ABLE Updated Dual Boot Configuration Mode section Removed RC delay to PROGRAMN workaround Updated I2C Configuration Mode s...

Page 55: ... during device configuration Updated Master and Slave SPI Configuration Port Pins section Added information on SN pin state when configuring in Slave SPI mode Updated I2C Configuration Mode section Added new EFB instantiation requirement for I2 C configuration port access per Product Bulletin PB1412 Updated Reading Flash Pages section Added information on retrieval delay Updated MachXO2 Flash Memo...

Page 56: ...nd 0xF8 in Step 3 of the MachXO2 Flash Memory Programming Flow diagram October 2013 02 7 Updated the Default State of the sysCONFIG Pins table September 2013 02 6 Updated the Default State of the sysCONFIG Pins table Added the Default State in Diamond for Each Port table August 2013 02 5 Updated Master SPI Configuration Mode MSPI section including the Master SPI Configuration Mode figure Updated t...

Page 57: ...amming Flow June 2012 02 0 Major update including Updated Programming algorithm Added Feature Row discussion Improved coverage of configuration port management February 2012 01 4 Document status changed from Advance to Final Updated document with new corporate logo August 2011 01 3 Added User SPI during transparent programming caution Added external SPI address for dual boot option May 2011 01 2 C...

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