MachXO2 Programming and Configuration Usage Guide
18
The JTAG port is enabled by default when the MachXO2 is in the Feature Row HW Default Mode state. Like all of
the other configuration port pins the JTAG pins can become general purpose I/O. Unlike the other ports, the default
state for the JTAG port is to remain active in user mode (i.e. ENABLE state). The JTAG pins can be recovered to be
general purpose I/O by setting the JTAG_PORT preference to the DISABLE state. It is recommended the JTAG
port remain dedicated programming pins.
The JTAG port, when set in the DISABLE state, enables the JTAGENB input. JTAGENB permits the JTAG pins to
be multiplexed. Asserting JTAGENB high causes the JTAG pins to take on the IEEE 1149.1 personality. De-assert-
ing JTAGENB (i.e. driven low) causes the JTAG port pins to become general purpose I/O. Design the JTAG port cir-
cuitry carefully when taking advantage of JTAG port pin multiplexing. Avoid bus contention between logic attached
to the JTAG port.
When the device is programmed through IEEE 1149.1 control, the sysCONFIG programming pins, such as DONE,
cannot be used to determine programming progress. This is because the state of the boundary scan cell will drive
the pin, per the IEEE JTAG standard, rather than normal internal logic.
Table 12. JTAG Port Pins
TDO: The Test Data Output (TDO) pin is used to shift out serial test instructions and data. When TDO is not being
driven by the internal circuitry, the pin will be in a high impedance state. The only time TDO is not in a high imped-
ance state is when the JTAG state machine is in the Shift IR or Shift DR state. This pin should be wired to TDO of
the JTAG connector, or to TDI of a downstream device in a JTAG chain. An internal pull-up resistor on the TDO pin
is provided. The internal resistor is pulled up to VCCIO Bank 0.
TDI: The Test Data Input (TDI) pin is used to shift in serial test instructions and data. This pin should be wired to
TDI of the JTAG connector, or to TDO of an upstream device in a JTAG chain. An internal pull-up resistor on the
TDI pin is provided. The internal resistor is pulled up to VCCIO of Bank 0.
TMS: The Test Mode Select (TMS) pin is an input pin that controls the progression through the 1149.1 compliant
state machine states. The TMS pin is sampled on the rising edge of TCK. The JTAG state machine remains in or
transitions to a new TAP state depending on the current state of the TAP, and the present state of the TMS input. An
internal pull-up resistor is present on TMS per the JTAG specification. The internal resistor is pulled to the VCCIO
of Bank 0.
TCK: The test clock pin (TCK) provides the clock used to time the other JTAG port pins. Data is shifted into the
instruction or data registers on the rising edge of TCK and shifted out on the falling edge of TCK. The TAP is a
static design permitting TCK to be stopped in either the high or low state. The maximum input frequency for TCK is
specified in the DC and Switching Characteristics section of DS1035,
. The TCK pin
does not have a pull-up. An external pull-down resistor of 4.7 kOhms is recommended to avoid inadvertently clock-
ing the TAP controller as power is applied to the MachXO2.
JTAGENB: The JTAG ENABLE pin, also known as the IEEE 1149.1 conformance pin, is an input pin that can be
used to multiplex the JTAG port. The JTAGENB pin is only active in user mode. The JTAGENB pin is a user I/O
while the JTAG port is in the ENABLE state. Figure 8 shows the default behavior of the JTAG port of a MachXO2
device.
Pin Name
Pin Function
(Configuration Mode)
Pin Direction
(Configuration Mode)
Default Function
(User Mode)
TDI
TDI
Input with weak pull-up
TDI
TDO
TDO
Output with weak pull-up
TDO
TCK
TCK
Input
TCK
TMS
TMS
Input with weak pull-up
TMS
JTAGENB
I/O
Input/output with weak pull-down
I/O
