MachXO2 Programming and Configuration Usage Guide
27
An external I
2
C master accesses the Configuration Logic using address 1000000 (7-bit mode) or 1111000000 (10-
bit mode) unless the EFB I
2
C base address has been modified. Use IPexpress, not Spreadsheet View, to modify
the address to which the Primary and Secondary I
2
C controllers respond. It is necessary to instantiate the EFB in
order to change the address. The address is shared by the Primary and Secondary I
2
C controllers.
Table 17 shows the address decoding used to access the I
2
C resources in the MachXO2.
Table 17. Slave Addresses for I
2
C Ports
1
The Primary I
2
C core can be used for accessing the User Flash Memory (UFM) and for programming the Configu-
ration Flash. However, the Primary I
2
C port cannot be used for both UFM/Configuration access and User functions
in the same design. The operation of the User Mode Primary and User Mode Secondary I
2
C controllers is
described in TN1205,
Using User Flash Memory and Hardened Control Functions in MachXO2 Devices
. Interact-
ing with these I
2
C slave devices is not covered in this document.
The fourth I
2
C resource in the MachXO2 is located at offset 3. In some instances an I
2
C memory transaction to the
configuration logic may be interrupted or abandoned. It is possible for a command to be accepted by the configura-
tion logic that causes the configuration logic to respond with data. In the event that the
I
2
C
memory transaction is
interrupted or abandoned, the configuration logic continues to return the queued data. New incoming I
2
C com-
mands may be considered padding bytes or may be misinterpreted. Clear this condition by writing any value to off-
set 3. The configuration logic command interpreter will reset, any queued data will be flushed, and subsequent I
2
C
memory transactions to the Configuration Logic will operate correctly.
WISHBONE Configuration Mode
The MachXO2 can access the Configuration Flash, User Flash Memory, and the Feature Row from an internal
WISHBONE bus. To use the WISHBONE bus the Embedded Function Block must be inserted into your design. You
design logic to interface to the EFB and then perform WISHBONE bus transactions to access resources attached
to the configuration logic.
Figure 14. WISHBONE Configuration Mode
Slave Address
I
2
C Function
yyyxxxxx
00
Primary I
2
C Controller Configuration Logic address. Always responds to 7-bit or 10-bit addresses.
yyyxxxxx
01
User Mode Primary I
2
C Controller address.
yyyxxxxx
10
User Mode Secondary I
2
C Controller address.
yyyxxxxx
11
Primary I
2
C Configuration Logic Reset. Always responds to 7-bit or 10-bit addresses.
1. Although there are eight possible combinations of the reserved address bits 1111 XXX, only the four combinations 1111 0XX are used for
10-bit addressing. The remaining four combinations 1111 1XX are reserved for future I2C-bus enhancements.
Flash
Memory
MachXO2
Logic
Configuration
Logic
WISHBONE
Interface
