MachXO2 Programming and Configuration Usage Guide
26
I
2
C Configuration Mode
The MachXO2 has an I
2
C Configuration port for use in accessing the configuration logic. An I
2
C master can com-
municate to the configuration logic using 10-bit or 7-bit addressing modes. The I
2
C SCL input can accept a clock
frequency up to 400 kHz. You can reprogram the Configuration Flash, UFM and Feature Row, and access sta-
tus/control registers within the configuration logic block. Reprogramming the Flash memories can be done either
offline or in transparent operations. You cannot directly update the configuration SRAM. It is necessary to send a
REFRESH command after reprogramming the Flash memory in order for the configuration SRAM to be updated.
Table 16. I
2
C Port Pins
The I
2
C Configuration port is available when the MachXO2 is in Feature Row HW Default Mode state (that is,
blank/erased). The default state set for the I2C_PORT in the Diamond design software is to place the I2C_PORT in
the DISABLE state. You must make sure the I2C_PORT is set to the ENABLE state to leave the I
2
C interface active
in user mode. Lattice recommends making a second configuration port available (e.g. JTAG) in order to recover
from erroneously disabling the I
2
C port.
Figure 13. I
2
C Configuration Logic
There are two hardened I
2
C controllers in a MachXO2 device, a primary and a secondary. The primary controller
provides an interface to the MachXO2 Configuration Logic, and access to Wishbone registers. Access to the Wish-
bone registers is referred to as User Mode I
2
C. The primary I
2
C controller is the only one that permits access to the
Configuration Logic. The Secondary I
2
C controller is always a User Mode I
2
C controller.
When the MachXO2 is in Feature Row HW Default Mode state the I
2
C port is enabled, and you may interact with
the primary I
2
C controller. Whenever the I
2
C port is enabled access to the Configuration Logic is possible. Instanti-
ate the Embedded Function Block (EFB) to enable I2C port access to the Configuration Logic in User Mode. More-
over, when instantiated, the EFB 'wb_clk_i'
input must be connected to a valid clock source of at least 7.5x the I
2
C
bus rate (for example, >3.0 MHz when
I
2
C
rate = 400 kHz).
The Primary I
2
C controller provides access to the Configuration Logic when:
• The MachXO2 is in Feature Row HW Default Mode state
• The EFB is instantiated with 'wb_clk_i' input connected to a valid clock source of at least 7.5x the I
2
C bus rate,
and the I
2
C port pins are in the ENABLE state
Pin Name
Description
SCL
I
2
C bus clock
SDA
I
2
C bus data line
Flash
Memory
MachXO2
Logic
Configuration
Logic
I
2
C
Interface
I
2
C
Master
2
