26
LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
Ordering Information
Description
Ordering Part Number
China RoHS Environment-Friendly
Use Period (EFUP)
LatticeECP3 Serial Protocol Board
LFE3-95E-SP-EVN
Known Issues
SATA Target interface(CN2) channel – Transmit data must be polarity-inverted in FPGA design for correct connec-
tion.
SATA Host interface(CN1) channel – Receive data must be polarity-inverted in FPGA design for correct connection.
Technical Support Assistance
Hotline:
1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail:
Internet:
www.latticesemi.com
Revision History
Date
Version
Change Summary
November 2009
01.0
Initial release.
January 2010
01.1
Updated DDR2 Memory Interface Connections table.
Updated schematic.
Updated Bill of Materials table.
May 2010
01.2
Added Known Issues section.
August 2012
01.3
Updated document with new corporate logo.
Updated Programming schematic.
November 2012
01.4
SERDES SMA Test Connectors table – Updated connector numbers.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at
www.latticesemi.com/legal
. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.