15
LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
allel Flash devices. Application note AN8077,
Parallel Flash Programming and FPGA Configuration
,
addresses
the use of the parallel Flash implementation.
On-Board Clock Capabilities
Dedicated SERDES Reference Clock Inputs
(see Appendix A, Figure 26)
• A 156.25 MHz, low-jitter (5x7.5mm surface mount) oscillator is included on-board.
– Connected via clock mux to PCSB_REFCLK
– Clock control CLOCK_CTRL_SEL0 is connected to both the FPGA (ball #A25) or the Crossover PLD (ball
#N6). Either of these sources selects the clock source of Y1 oscillator or J29 and J33 SMA inputs.
• A 125.00 MHz, low-jitter (5x7.5mm surface mount) oscillator is included on-board.
– Connected via clock mux to PCSC_REFCLK
– Clock control CLOCK_CTRL_SEL1 is connected to both the FPGA (ball #B25) or the Crossover PLD (ball
#M14). Either of these sources selects the clock source of Y2 oscillator or J30 and J34 SMA inputs.
***SMA connections J29 and J33 can provide an external clock source to PCSB. J29 is the true and J33 is the
compliment of the differential pair. The description markings on the evaluation board are incorrect.
***SMA connections J30 and J34 can provide an external clock source to PCSC. J30 is the true and J34 is the
compliment of the differential pair. The description markings on the evaluation board are incorrect.
User Defined General Purpose Clock Oscillator
(see Appendix A, Figure 31)
A 100 MHz oscillator is included on the board. It is fanned-out to several destinations on the board. They include
the following. This oscillator is used for general clocking and should be avoided for jitter sensitive applications.
Table 7. 100 MHz Clock Destinations
Clock Destination
Evaluation Board Designation
Destination Pin
Crossover PLD
U17
A8
FPGA
U1
B6
FPGA
U1
H17-PCLKT0
FPGA
U1
P30-RUM2_GPLLT_IN_A
(see Appendix A, Figure 33)
An auxiliary SMT oscillator area is included on the board. It includes a 5x7.5mm surface-mount pad for the addition
of any user-defined oscillator. This oscillator interconnects to FPGA ball numbers AB28 and AB29 that are specifi-
cally general purpose PLL inputs to the FPGA fabric.
(see Appendix A, Figure 33)
SMA inputs J38 and J39 are provided to drive any externally generated differential clock onto the board. These 50-
ohm terminated SMAs interconnect to FPGA ball numbers U28 and V28 that are specifically PCLKT3_0 and
PCLKC3_0 inputs to the FPGA fabric.
SERDES
Surface Mounted SMA Connections
(see Appendix A, Figure 26)
