Lattice Semiconductor LatticeECP3 Versa, User Manual

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LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
Table 25. 88E1111 Control and Status Interconnections to FPGA (see Appendix A, Figure 33)
PHY
Control/Status 88E1111 Pin
1156 fpBGA
Ball Number
MDIO M1 D20
MDC L3 F21
RESETn K3 F22
INTn L1 A21
FREQ_SEL H8 B21
CLK25 H9 D21
Crossover PLD Device
(see Appendix A, Figure 25, U17)
The board includes a Lattice LCMXO-1200C Crossover PLD which is used in conjunction with the parallel Flash
device for loading the configuration memory of the FPGA. It is also used for general-purpose board management
functions. It has several connections to the FPGA and other devices on the board and includes an active high,
push-button (SW4) if needed for user designs.
Generic user-defined interconnections are defined in Table 26.
Table 26. MachXO to FPGA Interconnections
MachXO
csBGA Ball Number
FPGA
fpBGA Ball Number
M1 C3
P13 C4
P10 B1
N7 B2
N8 E4
P11 D4
N13 B3
N1 A2
N3 D5
N4 C6
P1 B4
M12 A3
M2 D6
M3 C5
M4 A4
M6 A5
DDR2 Memory
(See Appendix A, Figure 30)
The board is equipped with two Micron MT47H16M16BG 16-bit DDR2 memory devices interfaced to a 32-bit DDR2
memory controller. The interface includes the termination to provide 266MHz DDR2 operations. The connections
between the FPGA memory devices are shown in Table 27.