21
LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
Table 19. Logic Analyzer To FPGA Pin Reference (See Appendix A, Figure 33)
Signal
1156 fpBGA Ball #
Signal
1156 fpBGA Ball #
LA1
G13
LA2
H14
LA3
A13
LA4
B13
LA5
D10
LA6
C10
LA7
C13
LA8
D13
LA9
J15
LA10
H15
LA11
D3
LA12
C2
LA13
C14
LA14
D14
LA15
A14
LA16
B14
LA17
G16
LA18
G17
LA19
D15
LA20
E15
LA21
J16
LA22
H16
LA23
A15
LA24
B15
LA25
E17
LA26
F28
LA27
C16
LA28
D16
LA29
K16
LA30
L16
LA31
A16
LA32
B16
LA33
G18
LA34
F19
10/100/1000Base Ethernet Interface
(see Appendix A, Figure 28, U21)
The Marvell 88E1111 Gigabit Ethernet transceiver device (U21) is included on the board. This physical layer device
supports 1000BASE-T, 100BASE-TX, and 10BASE-T applications via a standard Media interface to an RJ-45 (Bel
Stewart “MAGJACK” p/n L829-1J1T-43) connection. The RJ-45 connection includes network magnetics providing
the proper signal conditioning, electro-magnetic interference suppression and signal isolation. This connector
includes two LEDs and the board includes four status LEDs from the Marvell device. The LEDs are register-pro-
grammed and detailed descriptions are included in the Marvell data sheet.
Table 20. PHY Status Indicators
LED
Status Description
RJ45- Yellow
LED RX
RJ45- Orange
LED TX
PCB Amber (D16)
LINK 10
PCB Amber (D17)
LINK 100
PCB Green (D18)
LINK 100
PCB Amber (D19)
DUPLEX
The Marvell 88E1111 device communicates via a MAC interface to the LatticeECP3 device via GMII, SGMII, and a
standard 10-bit interface. The evaluation board includes the means to setup the required hardware configuration for
the PHY to operate in all the supported modes. Hardware configuration options such as PHY address, PHY operat-
ing mode, auto-negotiation, and physical connection type must be set up using the configuration switches SW7 to
SW13 on the back side of the board. These switches tie the CONFIG[6:0] pins to the control LED output pins. The
encoded values of the LED outputs that are tied to the CONFIG[6:0] pins are latched at the de-assertion of the
PHY RESETn control.
The switch matrix of the PHY CONFIG pins are described below. DIP switches control the hardware settings.
Note:
Only one switch position per DIP pack should be on for any configuration.