12
LatticeECP2M SERDES
Lattice Semiconductor
Evaluation Board User’s Guide
Figure 4. 17-Segment LED Display
Segment
BGA
A
B
C
D
E
F
G
H
K
M
N
P
R
S
T
U
DP
H2
J3
G1
H3
J7
H5
G5
G6
F3
J8
E1
J9
E3
F5
D3
F6
C2
A
B
C
D
G
F
E
DP
H
T S R
K M N
U
P
Test SMA Connections
General-purpose FPGA pins are available via SMA test connections. These connections are designed to permit
evaluations of several types of FPGA I/O buffers. The use of several termination schemes permits easy interfaces
for the type of buffer.
Table 12. FPGA I/O Test SMA Connectors (see Appendix A, Figure 9)
SMA
Designation
Name
LFE2M35E
Signal
672-BGA
Termination
Description
Termination
Resistor(s)
J37
LVDS_INP0
PR37A
N23
100-ohm Differential
R130
J39
LVDS_INN0
PR37B
M21
LVDS_INP1
PR41A
P24
100-ohm Differential
R132
LVDS_INN1
PR41B
P23
J45
LVDS_INP2
PR51A
T24
100-ohm Differential
R134
J47
LVDS_INN2
PR51B
U24
J49*
LVDS_INP3
PR57A
V24
100-ohm Differential
R136
J51*
LVDS_INN3
PR57B
W24
J38
LVDS_OUTP0
PR50A
T23
100-ohm Differential
R131
J40
LVDS_OUTN0
PR50B
T22
J42
LVDS_OUTP1
PR53A
V26
100-ohm Differential
R133
J44
LVDS_OUTN1
PR53B
V25
J46
LVDS_OUTP2
PR55A
W26
100-ohm Differential
R135
J48
LVDS_OUTN2
PR55B
W25
J50
LVDS_OUTP3
PR59A
Y26
100-ohm Differential
R137
J52
LVDS_OUTN3
PR59A
AA26