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LatticeECP2M SERDES
Lattice Semiconductor
Evaluation Board User’s Guide
Configuration Status Indicators
(see Appendix A, Figure 4)
These LEDs indicate the status of configuration to the FPGA.
• D8 (red) illuminated – Indicates that programming was aborted or reinitialized, driving the INITN output low.
• D11 (green) illuminated – Indicates the successful completion of configuration by releasing the open collector
DONE output pin.
• D12 (green) flashing – Indicates TDI activity.
• D10 (red) illuminated – Indicates that PROGRAMN is low.
• D9 (red) illuminated – Indicates that GSRN is low.
PROGRAMN and GSRN
(see Appendix A, Figure 4)
These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW3) and GSRN (SW2).
Depressing the button drives a logic level “0” to the device.
CFG [2:0]
(see Appendix A, Figure 4)
The FPGA CFG pins are set on the board for a particular programming mode via the SW1 DIP switch. JTAG pro-
gramming is independent of the MODE pins and is always available to the user.
On-Board Flash Memory
(see Appendix A, Figure 4)
Two memory devices (U10 and U12) are on-board for non-volatile configuration memory storage.
These two devices occupy the same Flash slot on the board. U10 can be populated with an 8M or smaller 8-pin
SOIC device. U12 can be used in place of U10 with a 16-pin TSSOP 64M Flash device.
U15 is supplied as an 8M Flash device.
J11 is used to control the selection of the Flash memory to be accessed.
FPGA Clock Management
(see Appendix A, Figure 8)
The evaluation board includes various features for generating and managing on-board clocks. The clocks are gen-
erated from input provided via SMAs (see Table 5) or from crystal oscillators (Y1 and Y2). Y1 is socketed for inter-
changeability and Y2 is a 100MHz surface-mounted oscillator which is fanned-out around U1 for reference clocks
with a fan-out buffer IC.
A 4-pin DIP type oscillator such as the Connor-Winfield XO-400 series can be used in socket Y1.
Both of these input clock sources are routed through the Lattice ispClock5620A programmable clock manager
devices (U2). These clock management devices allow for clock synthesis and buffering.
