Lattice Semiconductor LatticeECP2M SERDES, User Manual

Page: 10 / 25

10
LatticeECP2M SERDES
Lattice Semiconductor Evaluation Board User’s Guide
SERDES
(see Appendix A, Figure 5)
SERDES Reference Clock
The 50-ohm terminated SMA connectors provide supply reference clocks directly to the LatticeECP2M device from
the ispClock management device. This device drives clocks to both SERDES quads via 100-ohm LVDS signaling.
The on-board clock oscillators mentioned in previous sections of this document can be chosen to drive the same
SERDES reference clocks. In addition, the board can be provisioned to source the clock from the PCI Express
edge-fingers directly to the SERDES REFCLK pins.
SERDES Channels
Surface Mounted SMA Connections
(see Appendix A, Figure 5)
DC coupled top-mounted SMA connectors connect to the four SERDES Tx and Rx channels. These pins are
directly coupled to the designated SMA connector, creating a path for both input and output differential data.
Table 7. SERDES Connectors (see Appendix A, Figure 5)
SMA Channel Name SMA Channel Name
J18 U_HDINP0 J19 U_HDOUTP0
J21 U_HDINN0 J22 U_HDOUTN0
J24 U_HDINP1 J25 U_HDOUTP1
J26 U_HDINN1 J27 U_HDOUTN1
J29 U_HDINN2 J30 U_HDOUTP2
J32 U_HDINP2 J33 U_HDOUTN2
J20 U_HDINP3 J28 U_HDOUTP3
J23 U_HDINN3 J31 U_HDOUTN3
SERDES SFP Transceiver Interface
(see Appendix A, Figure 5)
A small form-factor pluggable (SFP) transceiver cage is included for evaluation of SFP specific protocols. The PCB
includes the appropriate power and high-speed circuitry needed for the SFP standard transceiver.
Note: this inter-
face is only available on boards featuring a LatticeECP2M-50 or larger FPGA.
Table 8. SFP Connections to SERDES Pins (see Appendix A, Figure 5)
SFP Rx Channel Name SFP Tx Channel Name
RD+ L_HDINP3 TD+ L_HDOUTP3
RD- L_HDINN3 TD- L_HDOUTN3
Table 9. SFP Control and Status Connections to FPGA
SFP Pin FPGA BGA SFP Pin FPGA BGA
TxFault M3 ModeDef0 N1
TxDis L8 ModeDef1 M1
LOS N2 ModeDef3 M6
RateSel N3