11
LatticeECP2M SERDES
Lattice Semiconductor
Evaluation Board User’s Guide
SERDES SATA Channels
(see Appendix A, Figure 5)
Connections are included to attach SATA type cables to SERDES channels for board-to-board or loopback pur-
poses. The connectors are configured using the 7-pin SATA specifications.
Note: this interface is only available on
boards featuring a LatticeECP2M-50 or larger FPGA.
Table 10. SERDES to SATA Connector
CN1 Pin
FPGA BGA
CN2 Pin
FPGA BGA
TxFault
M3
ModeDef0
N1
TxDis
L8
ModeDef1
M1
LOS
N2
ModeDef3
M6
RateSel
N3
SERDES PCI Express Channels
(see Appendix A, Figure 5)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge-
fingers (CN1) to fit directly into an x1 host receptacle. Power can be supplied directly from the PCI Express host via
the edge-finger connections.
Note: this interface is only available on boards featuring a LatticeECP2M-50 or larger
FPGA.
FPGA Test Pins
(see Appendix A, Figure 10)
General-purpose FPGA pins are available for user applications. FPGA pins are connected to switches and LEDS
designated according to the following table.
Table 11. FPGA Test Pins (see Appendix A, Figure 7)
Switch
BGA
Netname
LED
BGA
NetName
SW6D
T3
Switch1
D16
U3
RED1
SW6C
T4
Switch2
D17
U4
YELLOW1
SW6B
P8
Switch3
D19
U5
GREEN1
SW6A
R6
Switch4
D21
U6
BLUE1
SW5D
T1
Switch5
D15
U2
RED2
SW5C
U1
Switch6
D18
V1
YELLOW2
SW5B
R7
Switch7
D20
W2
GREEN2
SW5A
T5
Switch8
D22
V2
BLUE2
Note: LEDs will illuminate if connected to an un-programmed FPGA pin. It is recommended that a pull-down be
programmed on FPGA output pins.
17-Segment LED Display
(see Appendix A, Figure 10)
General-purpose FPGA pins are connected to a 17-segment display according to the following table. These pins
can be driven low to illuminate the display segments.