BT830 Hardware Integration Guide
Version 0.1 (PRELIMINARY)
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23
CONN-GUIDE-BT830
(PRELIMINARY)
Figure 15: Digital Audio Interface Master Timing
9
P
OWER
S
UPPLY AND
R
EGULATION
See the Example Application Schematic (Error! Reference source not found.) for the regulator configuration. BT830
can be powered by either two sources listed below
Method #1: Apply 3.3 V on pin-9,High-voltage linear regulator input (VREG_IN_HV), to generate the main 1.8
V out put on pin-10 (VREG_OUT_HV).
A minimum 1.5
μ
F capacitor must be connected to the Pin-10 (VREG_OUT_HV). Low ESR capacitors such as
multilayer ceramic types should be used.
Method #2: Apply 1.8V on pin-10 High-voltage linear regulator output (VREG_OUT_HV), to generate the
internal voltage for the system. Be sure to left Pin-9 un-connected in this method.
9.1
Voltage Regulator Enable and Reset
A single pin, VREG_EN_RST#, controls both the High-voltage linear regulator enables and the digital reset function.
The VREG_EN_RST# pin remains active controlling the reset function if the HV linear regulator is not used so the pin
must be driven high to take the device out of reset.
The regulator is enabled by taking the VREG_EN_RST# pin above 1V. The regulator can also be controlled by the
software.
The VREG_EN_RST# is also connected internally to the reset function, and is powered from the VDD_PADS supply, so
voltages above VDD_PADS must not be applied to this pin. The VREG_EN_RST# pin is pulled down internally.
The VREG_EN_RST# pin is an active low reset. Assert the reset signal for a period >5 ms to ensure a full reset.
Note: The regulator enables are released as soon as VREG_EN_RST# is low, so the regulators shut down.
Therefore do not take VREG_EN_RST# low for less than 5 ms, as a full reset is not guaranteed.
Other reset sources are:
Power-on reset
Via a software-configured watchdog timer
A warm reset function is also available under software control. After a warm reset the RAM data remains
available.
