BT830 Hardware Integration Guide
Version 0.1 (PRELIMINARY)
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CONN-GUIDE-BT830
(PRELIMINARY)
8.10
PCM_CLK and PCM_SYNC Generation
BT830 has two methods of generating PCM_CLK and PCM_SYNC in master mode:
Generating these signals by DDS from BT830internal 4MHz clock. Using this mode limits PCM_CLK to 128, 256
or 512 kHz and PCM_SYNC to 8 kHz.
Generating these signals by DDS from an internal 48MHz clock, which enables a greater range of frequencies
to be generated with low jitter but consumes more power. To select this second method set bit
48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the length
of PCM_SYNC is either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in
PSKEY_PCM_CONFIG32.
describes PCM_CLK frequency when generated from the internal 48MHz clock:
Equation 8.1: PCM_CLK Frequency Generated Using the Internal 48MHz Clock
Set the frequency of PCM_SYNC relative to PCM_CLK using
Equation 8.2: PCM_SYNC Frequency Relative to PCM_CLK
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to
generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set SKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.
8.11
PCM Configuration
Configure the PCM by using PSKEY_PCM_CONFIG32 and PSKEY_PCM_LOW_JITTER_CONFIG (See your PSKey file).
The default for PSKEY_PCM_CONFIG32 is 0x00800000 (for example: first slot following sync is active, 13-bit linear
voice format, long frame sync and interface master generating 256kHz PCM_CLK from 4MHz internal clock with no
tri-state of PCM_OUT).
8.12
Digital Audio Interface (I²S)
The digital audio interface supports the industry standard formats for I²S, left-justified or right-justified. The interface
shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage.
lists these alternative functions.
Table 12: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface.
PCM Interface
I²S Interface
PCM_OUT
SD_OUT
PCM_IN
SD_IN
PCM_SYNC
WS
PCM_CLK
SCK