KONTRON
Appendix A: System Resource Allocations
54
speedMOPSlcdCE User’s Guide
23.5
Peripheral Component Interconnect (PCI) Devices
All devices follow the PCI 2.1 specification. The BIOS and OS control memory and I/O resources.
Please refer to the PCI 2.1 specification for details.
PCI Device (IDSEL)
PCI IRQ
REQ/ GNT
Comment
AGP Graphic
-
-
Separate bus,
integrated in Intel chipset
Intel Ethernet (AD24)
INTE#
Discrete channel
Davicom Ethernet (AD17)
INTD#
REQ#3/GNT#3
PC/104-Plus allows 3 external
masters REQ#0, REQ#1 and
REQ#2
AC97 Sound
INTB#
Separate bus,
integrated in Intel chipset
1
st
UHCI USB Controller
INTA#
-
Separate bus,
integrated in Intel chipset
EHCI USB Controller
INTH#
Separate bus,
integrated in Intel chipset
23.6
SM Bus Devices
The speedMOPSlcdCE uses an onboard SM (System Management) Bus. This bus is not available on an
external connector.
The following SM Bus addresses are already used on the speedMOPSlcdCE.
SM Bus Address
SM Device
Comment
10h/11h
SM-Bus Host
Integrated in Intel ICH4
A0h/A1h
SPD EEPROM
Part of the DDR SDRAM module
D2h/D3h
Clock Generator
Note:
Accesses to the onboard SM Bus devices that are not allowed may cause system
failures. Problems resulting from this are not under warranty!
Summary of Contents for speedMOPSlcdCE
Page 1: ...speedMOPSlcdCE User s Guide Document Revision 1 2...
Page 2: ......
Page 8: ...KONTRON Contents vi speedMOPSlcdCEUser s Guide...
Page 86: ...KONTRON Appendix C Block Diagram 78 speedMOPSlcdCEUser s Guide 25 APPENDIX C BLOCK DIAGRAM...
Page 88: ...KONTRON Appendix D Mechanical Dimensions 80 speedMOPSlcdCEUser s Guide 26 1 2 Side View...
Page 90: ...KONTRON Appendix E Connector Layout 82 speedMOPSlcdCEUser s Guide 27 2 Bottom Side...
