Configuration
CP6003-SA
Page 4 - 12
ID 1044-9757, Rev. 2.0
P R E L I M I N A R Y
4.4.7
Board Interrupt Configuration Register (BICFG)
The Board Interrupt Configuration Register holds a series of bits defining the interrupt routing
for the Watchdog. If the Watchdog timer fails, it can generate an IRQ5 interrupt.
The enumeration signal is generated by a hot swap compatible board after insertion and prior
to removal. The system uses this interrupt signal to force software to configure the new board.
The derate signal indicates that the power supply is beginning to derate its power output.
Table 4-13: Board Interrupt Configuration Register (BICFG)
REGISTER NAME
BOARD INTERRUPT CONFIGURATION REGISTER (BICFG)
ADDRESS
0x286
BIT
NAME
DESCRIPTION
RESET
VALUE
ACCESS
7
Res.
Reserved
0
R/W
6
CFICF
CPCI fail signal interrupt configuration (FAL# signal):
0 = Disabled
1 = Enabled
0
R/W
5
CEICF
CPCI enumeration signal to IRQ5 routing (ENUM# signal):
0 = Disabled
1 = Enabled
0
R/W
4
CDICF
CPCI derate signal to IRQ5 routing (DEG# signal):
0 = Disabled
1 = Enabled
0
R/W
3 - 2
KICF
IPMI KCS interrupt configuration
00 = Disabled
01 = IRQ11
10 = IRQ10
11 = Reserved
00
R
1 - 0
WICF
Watchdog interrupt configuration:
00 = Disabled
01 = IRQ5
10 = Reserved
11 = Reserved
00
R/W
