D R A F T — F O R I N
T E R N A L U S E O N L Y
45
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User Guide
CP3010-SA
3.3.5 Watchdog Timer Control Register (W TIM)
Table 30: Watchdog Timer Control Register (WTIM)
ADDRESS
0x28C
BIT
7
6
5
4
3
2
1
0
NAME
WTE
WMD
WEN/WTR
WTM
ACCESS
R/W
R/W
R/W
R/W
RESET
0
00
0
0000
BITFIELD
DESCRIPTION
7
WTE
Watchdog timer expired status bit:
0 = Watchdog timer has not expired
1 = Watchdog timer has expired.
Writing a ’1’ to this bit resets it to 0.
6..5
WMD
Watchdog mode:
00 = Timer only mode
01 = Reset mode
10 = Interrupt mode
11 = Cascaded mode (dual-stage mode)
4
WEN/WTR
Watchdog enable / Watchdog trigger control bit:
0 = Watchdog timer not enabled
Prior to the Watchdog being enabled, this bit is known as WEN. After the Watchdog is
enabled, it is known as WTR. Once the Watchdog timer has been enabled, this bit can-
not be reset to 0. As long as the Watchdog timer is enabled, it will indicate a ’1’.
1 = Watchdog timer enabled
Writing a ’1’ to this bit causes the Watchdog to be retriggered to the timer value indicated
by bits WTM[3..0].
3..0
WTM
Watchdog timeout settings:
0000 = 0.125 s
1000 = 32 s
0001 = 0.25 s
1001 = 64 s
0010 = 0.5 s
1010 = 128 s
0011 = 1 s
1011 = 256 s
0100 = 2 s
1100 = 512 s
0101 = 4 s
1101 = 1024 s
0110 = 8 s
1110 = 2048 s
0111 = 16 s
1111 = 4096 s
