CP3002
Functional Description
ID 1042-9252, Rev. 2.0
Page 2 - 3
P R E L I M I N A R Y
2.
Functional Description
2.1
Processor
The board supports the Intel® Core™ i7-610E processor with 2.53 GHz clock speed, the Intel®
Core™ i7-620LE processor with 2.0 GHz clock speed, the Intel® Core™ i7-660UE processor
with 1.33 GHz clock speed, and the Intel® Celeron® U3405 processor with 1.07 GHz clock
speed.
The processor used on the CP3002 includes an integrated high-performance graphics control-
ler and a DDR3 dual-channel memory controller with ECC support as well as one x16 PCI Ex-
press 2.0 port operating at 2.5 GT/s. They support various technologies, such as:
•
Intel® Hyper-Threading Technology (Core™ i7)
•
Intel® Turbo Boost Technology (Core™ i7)
•
Intel® Intelligent Power Sharing (Core™ i7)
•
Intel® SpeedStep® Technology
•
Intel® Virtualization Technology
•
Intel® Streaming SIMD Extensions 4.1
•
Intel® Streaming SIMD Extensions 4.2
•
Intel® 64 Architecture
•
Execute Disable Bit
The Intel® Hyper-Threading Technology allows one execution core to function as two logical
processors. When this feature is enabled in the uEFI BIOS, four processor cores are present
to the operating system. This results in higher processing throughput and improved perfor-
mance on the multithreaded software.
The Intel® Turbo Boost Technology and the Intel® Intelligent Power Sharing technology allow
the processor and the graphics controller to opportunistically and automatically run faster than
its rated operating clock frequency if it is operating below power, temperature, and current lim-
its.
The Intel® SpeedStep® technology enables real-time dynamic switching of the voltage and fre-
quency between several modes. This is achieved by switching the bus ratios, the core operat-
ing voltage, and the core processor speeds without resetting the system.
The Intel® Core™ i7 processors used with the CP3002 have the following multi-level cache
structure:
•
64 kB L1 cache for each core
•
32 kB instruction cache
•
32 kB data cache
•
256 kB L2 instruction/data cache for each core
•
4 MB L3 shared instruction/data cache shared between both cores
The Intel® Celeron® processor used with the CP3002 has the following multi-level cache
structure:
•
64 kB L1 cache for each core
•
32 kB instruction cache
•
32 kB data cache
•
512 kB L2 instruction/data cache for each core
•
2 MB L3 shared instruction/data cache shared between both cores
