COMe-bEP7 Module User Guide
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3.4.
USB
USB 3.0 ports are backwards compatible with the USB 2.0 specification. The COMe-
bEP7 allows a maximum of four USB 3.0 (USB 2.0) ports.
Table 6: Supported USB Features
USB 3.0 Ports
up to 4x USB 3.0
USB 2.0 Ports
up to 4x USB 2.0
USB Over Current
Signals
2x
3.5.
PCI Express Configuration
The EPYC 3000 processor has up to 64 high speed lanes from the SoC, used for PCIe,
SATA and Ethernet. On SP4 SKUs all 32 lanes to COMe interface are available. With
SP4r2 only 24 lanes are available (Lanes 8 to 15 are not used).
COMe PCIe #0 to
COMe PCIe #7 can be bifurcated in x8, x4, x2, or x1.
COMe PCIe #8 to
COMe PCIe #15 can be bifurcated in x8, x4, x2, or x1. Only
available with SP4 (dual Die).
COMe PCIe #16 to
COMe PCIe #31 can be bifurcated in x16 , x8 or x4.
3.5.1.
AMD restrictions associated with the links
There are a maximum of 8 PCIe ports in any x16 link. A x16 link cannot be
connected to more than 8 PCIe devices.
Any 8 lane subset (lanes [15:8] or [7:0]) of a x16 link cannot be configured to
contain more than 7 ports.
All PCIe links that are a subset of a given x16 link must be aligned to their natural
bit boundaries. For example,
x8 links can only contain lanes [15:8] and [7:0].
x4 links can only contain lanes [15:12], [11:8], [7:4] and [3:0].
x2 links can only contain lanes [15:14], [13:12], [11:10], [9:8], [7:6], [5:4], [3:2], [1:0].
3.5.2.
Enabling COMe-bEP7 PCIe Links Configuration
Setup Options are available in the BIOS Menu for PCIe Links Configuration in BIOS
menu.
UEFI Setup Menu: Advanced
→
AMD PBS
