27
Intel® QuickPath Memory Controller
The Intel® Xeon® Processor 5600 Series has an integrated memory controller in its
package. The Intel® QuickPath Memory Controller supports DDR3 800, DDR3 1066 and DDR3
1333 memory technologies. The memory controller requires the following configuration
rules:
•
Both registered DIMMs (RDIMMs) and unbuffered DIMMs (UDIMMs)
•
RDIMMs must be ECC only, while UDIMMs can be ECC or non-ECC
•
RDIMMs and UDIMMs cannot be mixed
•
ECC and non-ECC UDIMMs can be mixed, but the presence of a single, non-ECC UDIMM
disables ECC functionality
•
Channel Independent mode is the only memory RAS mode that supports non-ECC DIMMs.
•
DIMMs with different timing parameters can be installed on different slots within the
same channel. But the timing that supports the slowest DIMM is applied to all. As a
consequence, faster DIMMs operate at timings supported by the slowest DIMM populated.
The same interface frequency is applied to all DIMMs on all channels.
Supported Memory
The Intel® Server Board T5520UR supports six DDR3 memory channels (three per processor
socket) with two DIMMs per channel. Up to 12 DIMMs can be used with dual-processor
sockets giving a maximum memory capacity of 96 GB.
The server board supports DDR3 800, DDR3 1066, and DDR3 1333 memory technologies.
Memory modules of mixed speed are supported by automatic selection of the highest
common frequency of all memory modules.
Publishing System Memory
The BIOS displays the “Total Memory” of the system on the diagnostic screen at the end
of POST if “Display Logo” is disabled in the BIOS setup. This is the total size of
memory discovered by the BIOS during POST and it is the sum of the individual
installed DDR3 DIMMs in the system. The BIOS provides the total memory of the system
in the main page of the BIOS setup.
The BIOS displays the “Effective Memory” of the system in the BIOS setup. The term
“Effective Memory”
refers to the total size of all DDR3 DIMMs that are active (not
disabled) and not used as redundant units.
Memory Map and Population Rules
The nomenclature for DIMM sockets implemented on the Intel® Server Board T5520UR is
shown in Table X.
Table 3. Memory Map
Processor Socket 1
Processor Socket 2
Channel
A
Channel
B
Channel
C
Channel
D
Channel
E
Channel
F
A1
A2
B1
B2
C1
C2
D1
D2 E1
E2
F1
F2
Memory Population Rules
The T5520UR server board memory is implemented according to the following rules
•
DIMMs are organized into physical slots on DDR3 memory channels that belong to
processor sockets.
•
The memory channels from processor socket 1 are identified as Channel A, B, and C.
The memory channels from processor socket 2 are identified as Channel D, E, and F.
