DV-5050M/5900M/DVF-J6050/J6050-G
15
CIRCUIT DESCRIPTION
Port No.
Port Name
I/O
Function
120,130
AVDD(1,0)
-
Analog supply voltage (+3.3V) for DAC.
121
VREFG
I
DAC reference voltage input for Cb signal.
122
IREFG
I
DAC bias current setting port for Cb signal.
123
COMPG
I
Capacitance connection for DAC (Cb signal) stabilization.
124
VGBOUT
O
Cb signal output for DAC.(Unused)
125,135
AVSS(0,1)
-
Analog ground for DAC.
126
VREFC
I
DAC reference voltage input for Cr, C signal.
127
IREFC
I
DAC bias current setting port for Cr, C signal.
128
COMPC
I
Capacitance connection for DAC (Cr, C signal) stabilization.
129
VCOUT
O
Unused.
131
VREFY
I
DAC reference voltage input for Y signal.
132
IREFY
I
DAC bias current setting port for Y signal.
133
COMPY
I
Capacitance connection for DAC (Y signal) stabilization.
134
VYOUT
O
Y signal output for DAC.
136
NC
-
Unused.
137
ACKIO
-
Connected to digital ground.
138
MODE121
I
Connected to digital ground.
139
PLLTEST
I
Connected to digital ground.
140,141
TESTSEL1,0
-
Test mode terminal. L : Fixed
142
DCTEST
-
DC test mode terminal.
143
XYSYNCO
I/O
Vertical synchronizing signal input/output.
144
XHSYNCO
I/O
Horizontal synchronizing signal input/output.
145
VCLK
O
Clock output for digital video data output.
147~150,152~155
VD0~VD7
O
Digital video data output (0~7)
158,159,161,162,
164,165,167,168,
MDQ0~MDQ15
I/O
SDRAM data bus (0~15).
170,171,173,175,
177,178,180181
183
MCKI
I
Clock input from SDRAM.
185
MCK
O
Clock output to SDRAM.
187
DQMLE
O
Lower bite data, mask signal of expander SDRAM.
189
DQMLM
O
Lower bite data, mask signal of main SDRAM.
190
DQMUE
O
Upper bite data, mask signal of expander SDRAM.
192
DQMUM
O
Upper bite data, mask signal of main SDRAM.
193
XWE
O
Write enable signal of SDRAM.
O
CAS signal of SDRAM.
O
RAS signal of SDRAM.
O
Chip select signal of expander SDARM.
O
Chip select signal of main SDARM.
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